iew_impl.hh (6658:f4de76601762) | iew_impl.hh (7598:c0ae58952ed0) |
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1/* | 1/* |
2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * |
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2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright --- 1570 unchanged lines hidden (view full) --- 1580 if (inst->isMemRef()) { 1581 iewExecutedRefs[tid]++; 1582 1583 if (inst->isLoad()) { 1584 iewExecLoadInsts[tid]++; 1585 } 1586 } 1587} | 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright --- 1570 unchanged lines hidden (view full) --- 1592 if (inst->isMemRef()) { 1593 iewExecutedRefs[tid]++; 1594 1595 if (inst->isLoad()) { 1596 iewExecLoadInsts[tid]++; 1597 } 1598 } 1599} |
1600 1601template <class Impl> 1602void 1603DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst) 1604{ 1605 ThreadID tid = inst->threadNumber; 1606 1607 if (!fetchRedirect[tid] || 1608 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1609 1610 if (inst->mispredicted()) { 1611 fetchRedirect[tid] = true; 1612 1613 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1614 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 1615 inst->readPredPC(), inst->readPredNPC()); 1616 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 1617 " NPC: %#x.\n", inst->readNextPC(), 1618 inst->readNextNPC()); 1619 // If incorrect, then signal the ROB that it must be squashed. 1620 squashDueToBranch(inst, tid); 1621 1622 if (inst->readPredTaken()) { 1623 predictedTakenIncorrect++; 1624 } else { 1625 predictedNotTakenIncorrect++; 1626 } 1627 } 1628 } 1629} |
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