iew_impl.hh (3970:d54945bab95d) | iew_impl.hh (4033:7bb1223f9645) |
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1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 1139 unchanged lines hidden (view full) --- 1148 } 1149 1150 toRename->iewInfo[tid].dispatchedToLSQ++; 1151 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 1152 // Same as non-speculative stores. 1153 inst->setCanCommit(); 1154 instQueue.insertBarrier(inst); 1155 add_to_iq = false; | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 1139 unchanged lines hidden (view full) --- 1148 } 1149 1150 toRename->iewInfo[tid].dispatchedToLSQ++; 1151 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 1152 // Same as non-speculative stores. 1153 inst->setCanCommit(); 1154 instQueue.insertBarrier(inst); 1155 add_to_iq = false; |
1156 } else if (inst->isNonSpeculative()) { 1157 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 1158 "encountered, skipping.\n", tid); 1159 1160 // Same as non-speculative stores. 1161 inst->setCanCommit(); 1162 1163 // Specifically insert it as nonspeculative. 1164 instQueue.insertNonSpec(inst); 1165 1166 ++iewDispNonSpecInsts; 1167 1168 add_to_iq = false; | |
1169 } else if (inst->isNop()) { 1170 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 1171 "skipping.\n", tid); 1172 1173 inst->setIssued(); 1174 inst->setExecuted(); 1175 inst->setCanCommit(); 1176 --- 11 unchanged lines hidden (view full) --- 1188 inst->setCanCommit(); 1189 1190 instQueue.recordProducer(inst); 1191 1192 add_to_iq = false; 1193 } else { 1194 add_to_iq = true; 1195 } | 1156 } else if (inst->isNop()) { 1157 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 1158 "skipping.\n", tid); 1159 1160 inst->setIssued(); 1161 inst->setExecuted(); 1162 inst->setCanCommit(); 1163 --- 11 unchanged lines hidden (view full) --- 1175 inst->setCanCommit(); 1176 1177 instQueue.recordProducer(inst); 1178 1179 add_to_iq = false; 1180 } else { 1181 add_to_iq = true; 1182 } |
1183 if (inst->isNonSpeculative()) { 1184 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 1185 "encountered, skipping.\n", tid); |
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1196 | 1186 |
1187 // Same as non-speculative stores. 1188 inst->setCanCommit(); 1189 1190 // Specifically insert it as nonspeculative. 1191 instQueue.insertNonSpec(inst); 1192 1193 ++iewDispNonSpecInsts; 1194 1195 add_to_iq = false; 1196 } 1197 |
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1197 // If the instruction queue is not full, then add the 1198 // instruction. 1199 if (add_to_iq) { 1200 instQueue.insert(inst); 1201 } 1202 1203 insts_to_dispatch.pop(); 1204 --- 169 unchanged lines hidden (view full) --- 1374 squashDueToBranch(inst, tid); 1375 1376 if (inst->readPredTaken()) { 1377 predictedTakenIncorrect++; 1378 } else { 1379 predictedNotTakenIncorrect++; 1380 } 1381 } else if (ldstQueue.violation(tid)) { | 1198 // If the instruction queue is not full, then add the 1199 // instruction. 1200 if (add_to_iq) { 1201 instQueue.insert(inst); 1202 } 1203 1204 insts_to_dispatch.pop(); 1205 --- 169 unchanged lines hidden (view full) --- 1375 squashDueToBranch(inst, tid); 1376 1377 if (inst->readPredTaken()) { 1378 predictedTakenIncorrect++; 1379 } else { 1380 predictedNotTakenIncorrect++; 1381 } 1382 } else if (ldstQueue.violation(tid)) { |
1383 assert(inst->isMemRef()); |
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1382 // If there was an ordering violation, then get the 1383 // DynInst that caused the violation. Note that this 1384 // clears the violation signal. 1385 DynInstPtr violator; 1386 violator = ldstQueue.getMemDepViolator(tid); 1387 1388 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 1389 "%#x, inst PC: %#x. Addr is: %#x.\n", 1390 violator->readPC(), inst->readPC(), inst->physEffAddr); 1391 1392 // Ensure the violating instruction is older than 1393 // current squash | 1384 // If there was an ordering violation, then get the 1385 // DynInst that caused the violation. Note that this 1386 // clears the violation signal. 1387 DynInstPtr violator; 1388 violator = ldstQueue.getMemDepViolator(tid); 1389 1390 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 1391 "%#x, inst PC: %#x. Addr is: %#x.\n", 1392 violator->readPC(), inst->readPC(), inst->physEffAddr); 1393 1394 // Ensure the violating instruction is older than 1395 // current squash |
1394 if (fetchRedirect[tid] && 1395 violator->seqNum >= toCommit->squashedSeqNum[tid]) | 1396/* if (fetchRedirect[tid] && 1397 violator->seqNum >= toCommit->squashedSeqNum[tid] + 1) |
1396 continue; | 1398 continue; |
1397 | 1399*/ |
1398 fetchRedirect[tid] = true; 1399 1400 // Tell the instruction queue that a violation has occured. 1401 instQueue.violation(inst, violator); 1402 1403 // Squash. 1404 squashDueToMemOrder(inst,tid); 1405 1406 ++memOrderViolationEvents; 1407 } else if (ldstQueue.loadBlocked(tid) && 1408 !ldstQueue.isLoadBlockedHandled(tid)) { 1409 fetchRedirect[tid] = true; 1410 1411 DPRINTF(IEW, "Load operation couldn't execute because the " 1412 "memory system is blocked. PC: %#x [sn:%lli]\n", 1413 inst->readPC(), inst->seqNum); 1414 1415 squashDueToMemBlocked(inst, tid); 1416 } | 1400 fetchRedirect[tid] = true; 1401 1402 // Tell the instruction queue that a violation has occured. 1403 instQueue.violation(inst, violator); 1404 1405 // Squash. 1406 squashDueToMemOrder(inst,tid); 1407 1408 ++memOrderViolationEvents; 1409 } else if (ldstQueue.loadBlocked(tid) && 1410 !ldstQueue.isLoadBlockedHandled(tid)) { 1411 fetchRedirect[tid] = true; 1412 1413 DPRINTF(IEW, "Load operation couldn't execute because the " 1414 "memory system is blocked. PC: %#x [sn:%lli]\n", 1415 inst->readPC(), inst->seqNum); 1416 1417 squashDueToMemBlocked(inst, tid); 1418 } |
1419 } else { 1420 // Reset any state associated with redirects that will not 1421 // be used. 1422 if (ldstQueue.violation(tid)) { 1423 assert(inst->isMemRef()); 1424 1425 DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 1426 1427 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 1428 "%#x, inst PC: %#x. Addr is: %#x.\n", 1429 violator->readPC(), inst->readPC(), inst->physEffAddr); 1430 DPRINTF(IEW, "Violation will not be handled because " 1431 "already squashing\n"); 1432 1433 ++memOrderViolationEvents; 1434 } 1435 if (ldstQueue.loadBlocked(tid) && 1436 !ldstQueue.isLoadBlockedHandled(tid)) { 1437 DPRINTF(IEW, "Load operation couldn't execute because the " 1438 "memory system is blocked. PC: %#x [sn:%lli]\n", 1439 inst->readPC(), inst->seqNum); 1440 DPRINTF(IEW, "Blocked load will not be handled because " 1441 "already squashing\n"); 1442 1443 ldstQueue.setLoadBlockedHandled(tid); 1444 } 1445 |
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1417 } 1418 } 1419 1420 // Update and record activity if we processed any instructions. 1421 if (inst_num) { 1422 if (exeStatus == Idle) { 1423 exeStatus = Running; 1424 } --- 133 unchanged lines hidden (view full) --- 1558 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 1559 } 1560 1561 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 1562 1563 //DPRINTF(IEW,"NonspecInst from thread %i",tid); 1564 if (fromCommit->commitInfo[tid].uncached) { 1565 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); | 1446 } 1447 } 1448 1449 // Update and record activity if we processed any instructions. 1450 if (inst_num) { 1451 if (exeStatus == Idle) { 1452 exeStatus = Running; 1453 } --- 133 unchanged lines hidden (view full) --- 1587 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 1588 } 1589 1590 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 1591 1592 //DPRINTF(IEW,"NonspecInst from thread %i",tid); 1593 if (fromCommit->commitInfo[tid].uncached) { 1594 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); |
1595 fromCommit->commitInfo[tid].uncachedLoad->setAtCommit(); |
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1566 } else { 1567 instQueue.scheduleNonSpec( 1568 fromCommit->commitInfo[tid].nonSpecSeqNum); 1569 } 1570 } 1571 1572 if (broadcast_free_entries) { 1573 toFetch->iewInfo[tid].iqCount = --- 66 unchanged lines hidden --- | 1596 } else { 1597 instQueue.scheduleNonSpec( 1598 fromCommit->commitInfo[tid].nonSpecSeqNum); 1599 } 1600 } 1601 1602 if (broadcast_free_entries) { 1603 toFetch->iewInfo[tid].iqCount = --- 66 unchanged lines hidden --- |