iew_impl.hh (3876:127c71cfe21a) | iew_impl.hh (3949:b6664282d899) |
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1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 467 unchanged lines hidden (view full) --- 476 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum); 477 478 toCommit->squash[tid] = true; 479 toCommit->squashedSeqNum[tid] = inst->seqNum; 480 toCommit->mispredPC[tid] = inst->readPC(); 481 toCommit->branchMispredict[tid] = true; 482 483#if ISA_HAS_DELAY_SLOT | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 467 unchanged lines hidden (view full) --- 476 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum); 477 478 toCommit->squash[tid] = true; 479 toCommit->squashedSeqNum[tid] = inst->seqNum; 480 toCommit->mispredPC[tid] = inst->readPC(); 481 toCommit->branchMispredict[tid] = true; 482 483#if ISA_HAS_DELAY_SLOT |
484 bool branch_taken = inst->readNextNPC() != 485 (inst->readNextPC() + sizeof(TheISA::MachInst)); | 484 int instSize = sizeof(TheISA::MachInst); 485 bool branch_taken = 486 !(inst->readNextPC() + instSize == inst->readNextNPC() && 487 (inst->readNextPC() == inst->readPC() + instSize || 488 inst->readNextPC() == inst->readPC() + 2 * instSize)); 489 DPRINTF(Sparc, "Branch taken = %s [sn:%i]\n", 490 branch_taken ? "true": "false", inst->seqNum); |
486 487 toCommit->branchTaken[tid] = branch_taken; 488 | 491 492 toCommit->branchTaken[tid] = branch_taken; 493 |
489 toCommit->condDelaySlotBranch[tid] = inst->isCondDelaySlot(); 490 491 if (inst->isCondDelaySlot() && branch_taken) { | 494 bool squashDelaySlot = true; 495// (inst->readNextPC() != inst->readPC() + sizeof(TheISA::MachInst)); 496 DPRINTF(Sparc, "Squash delay slot = %s [sn:%i]\n", 497 squashDelaySlot ? "true": "false", inst->seqNum); 498 toCommit->squashDelaySlot[tid] = squashDelaySlot; 499 //If we're squashing the delay slot, we need to pick back up at NextPC. 500 //Otherwise, NextPC isn't being squashed, so we should pick back up at 501 //NextNPC. 502 if (squashDelaySlot) { |
492 toCommit->nextPC[tid] = inst->readNextPC(); | 503 toCommit->nextPC[tid] = inst->readNextPC(); |
493 } else { | 504 toCommit->nextNPC[tid] = inst->readNextNPC(); 505 } else |
494 toCommit->nextPC[tid] = inst->readNextNPC(); | 506 toCommit->nextPC[tid] = inst->readNextNPC(); |
495 } | |
496#else 497 toCommit->branchTaken[tid] = inst->readNextPC() != 498 (inst->readPC() + sizeof(TheISA::MachInst)); 499 toCommit->nextPC[tid] = inst->readNextPC(); 500#endif 501 502 toCommit->includeSquashInst[tid] = false; 503 --- 5 unchanged lines hidden (view full) --- 509DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid) 510{ 511 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 512 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 513 514 toCommit->squash[tid] = true; 515 toCommit->squashedSeqNum[tid] = inst->seqNum; 516 toCommit->nextPC[tid] = inst->readNextPC(); | 507#else 508 toCommit->branchTaken[tid] = inst->readNextPC() != 509 (inst->readPC() + sizeof(TheISA::MachInst)); 510 toCommit->nextPC[tid] = inst->readNextPC(); 511#endif 512 513 toCommit->includeSquashInst[tid] = false; 514 --- 5 unchanged lines hidden (view full) --- 520DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid) 521{ 522 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 523 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 524 525 toCommit->squash[tid] = true; 526 toCommit->squashedSeqNum[tid] = inst->seqNum; 527 toCommit->nextPC[tid] = inst->readNextPC(); |
528#if ISA_HAS_DELAY_SLOT 529 toCommit->nextNPC[tid] = inst->readNextNPC(); 530#endif |
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517 toCommit->branchMispredict[tid] = false; 518 519 toCommit->includeSquashInst[tid] = false; 520 521 wroteToTimeBuffer = true; 522} 523 524template<class Impl> 525void 526DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid) 527{ 528 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 529 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 530 531 toCommit->squash[tid] = true; 532 toCommit->squashedSeqNum[tid] = inst->seqNum; 533 toCommit->nextPC[tid] = inst->readPC(); | 531 toCommit->branchMispredict[tid] = false; 532 533 toCommit->includeSquashInst[tid] = false; 534 535 wroteToTimeBuffer = true; 536} 537 538template<class Impl> 539void 540DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid) 541{ 542 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 543 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 544 545 toCommit->squash[tid] = true; 546 toCommit->squashedSeqNum[tid] = inst->seqNum; 547 toCommit->nextPC[tid] = inst->readPC(); |
548#if ISA_HAS_DELAY_SLOT 549 toCommit->nextNPC[tid] = inst->readNextNPC(); 550#endif |
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534 toCommit->branchMispredict[tid] = false; 535 536 // Must include the broadcasted SN in the squash. 537 toCommit->includeSquashInst[tid] = true; 538 539 ldstQueue.setLoadBlockedHandled(tid); 540 541 wroteToTimeBuffer = true; --- 124 unchanged lines hidden (view full) --- 666} 667 668template<class Impl> 669int 670DefaultIEW<Impl>::skidCount() 671{ 672 int max=0; 673 | 551 toCommit->branchMispredict[tid] = false; 552 553 // Must include the broadcasted SN in the squash. 554 toCommit->includeSquashInst[tid] = true; 555 556 ldstQueue.setLoadBlockedHandled(tid); 557 558 wroteToTimeBuffer = true; --- 124 unchanged lines hidden (view full) --- 683} 684 685template<class Impl> 686int 687DefaultIEW<Impl>::skidCount() 688{ 689 int max=0; 690 |
674 std::list<unsigned>::iterator threads = activeThreads->begin(); 675 std::list<unsigned>::iterator end = activeThreads->end(); | 691 std::list<unsigned>::iterator threads = (*activeThreads).begin(); |
676 | 692 |
677 while (threads != end) { 678 unsigned tid = *threads++; 679 unsigned thread_count = skidBuffer[tid].size(); | 693 while (threads != (*activeThreads).end()) { 694 unsigned thread_count = skidBuffer[*threads++].size(); |
680 if (max < thread_count) 681 max = thread_count; 682 } 683 684 return max; 685} 686 687template<class Impl> 688bool 689DefaultIEW<Impl>::skidsEmpty() 690{ | 695 if (max < thread_count) 696 max = thread_count; 697 } 698 699 return max; 700} 701 702template<class Impl> 703bool 704DefaultIEW<Impl>::skidsEmpty() 705{ |
691 std::list<unsigned>::iterator threads = activeThreads->begin(); 692 std::list<unsigned>::iterator end = activeThreads->end(); | 706 std::list<unsigned>::iterator threads = (*activeThreads).begin(); |
693 | 707 |
694 while (threads != end) { 695 unsigned tid = *threads++; 696 697 if (!skidBuffer[tid].empty()) | 708 while (threads != (*activeThreads).end()) { 709 if (!skidBuffer[*threads++].empty()) |
698 return false; 699 } 700 701 return true; 702} 703 704template <class Impl> 705void 706DefaultIEW<Impl>::updateStatus() 707{ 708 bool any_unblocking = false; 709 | 710 return false; 711 } 712 713 return true; 714} 715 716template <class Impl> 717void 718DefaultIEW<Impl>::updateStatus() 719{ 720 bool any_unblocking = false; 721 |
710 std::list<unsigned>::iterator threads = activeThreads->begin(); 711 std::list<unsigned>::iterator end = activeThreads->end(); | 722 std::list<unsigned>::iterator threads = (*activeThreads).begin(); |
712 | 723 |
713 while (threads != end) { | 724 threads = (*activeThreads).begin(); 725 726 while (threads != (*activeThreads).end()) { |
714 unsigned tid = *threads++; 715 716 if (dispatchStatus[tid] == Unblocking) { 717 any_unblocking = true; 718 break; 719 } 720 } 721 --- 397 unchanged lines hidden (view full) --- 1119 add_to_iq = false; 1120 1121 ++iewDispNonSpecInsts; 1122 } else { 1123 add_to_iq = true; 1124 } 1125 1126 toRename->iewInfo[tid].dispatchedToLSQ++; | 727 unsigned tid = *threads++; 728 729 if (dispatchStatus[tid] == Unblocking) { 730 any_unblocking = true; 731 break; 732 } 733 } 734 --- 397 unchanged lines hidden (view full) --- 1132 add_to_iq = false; 1133 1134 ++iewDispNonSpecInsts; 1135 } else { 1136 add_to_iq = true; 1137 } 1138 1139 toRename->iewInfo[tid].dispatchedToLSQ++; |
1140#if FULL_SYSTEM |
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1127 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 1128 // Same as non-speculative stores. 1129 inst->setCanCommit(); 1130 instQueue.insertBarrier(inst); 1131 add_to_iq = false; | 1141 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 1142 // Same as non-speculative stores. 1143 inst->setCanCommit(); 1144 instQueue.insertBarrier(inst); 1145 add_to_iq = false; |
1146#endif |
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1132 } else if (inst->isNonSpeculative()) { 1133 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 1134 "encountered, skipping.\n", tid); 1135 1136 // Same as non-speculative stores. 1137 inst->setCanCommit(); 1138 1139 // Specifically insert it as nonspeculative. --- 83 unchanged lines hidden (view full) --- 1223 1224template <class Impl> 1225void 1226DefaultIEW<Impl>::executeInsts() 1227{ 1228 wbNumInst = 0; 1229 wbCycle = 0; 1230 | 1147 } else if (inst->isNonSpeculative()) { 1148 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 1149 "encountered, skipping.\n", tid); 1150 1151 // Same as non-speculative stores. 1152 inst->setCanCommit(); 1153 1154 // Specifically insert it as nonspeculative. --- 83 unchanged lines hidden (view full) --- 1238 1239template <class Impl> 1240void 1241DefaultIEW<Impl>::executeInsts() 1242{ 1243 wbNumInst = 0; 1244 wbCycle = 0; 1245 |
1231 std::list<unsigned>::iterator threads = activeThreads->begin(); 1232 std::list<unsigned>::iterator end = activeThreads->end(); | 1246 std::list<unsigned>::iterator threads = (*activeThreads).begin(); |
1233 | 1247 |
1234 while (threads != end) { | 1248 while (threads != (*activeThreads).end()) { |
1235 unsigned tid = *threads++; 1236 fetchRedirect[tid] = false; 1237 } 1238 1239 // Uncomment this if you want to see all available instructions. 1240// printAvailableInsts(); 1241 1242 // Execute/writeback any instructions that are available. --- 93 unchanged lines hidden (view full) --- 1336 1337 if (!fetchRedirect[tid] || 1338 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1339 1340 if (inst->mispredicted()) { 1341 fetchRedirect[tid] = true; 1342 1343 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); | 1249 unsigned tid = *threads++; 1250 fetchRedirect[tid] = false; 1251 } 1252 1253 // Uncomment this if you want to see all available instructions. 1254// printAvailableInsts(); 1255 1256 // Execute/writeback any instructions that are available. --- 93 unchanged lines hidden (view full) --- 1350 1351 if (!fetchRedirect[tid] || 1352 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1353 1354 if (inst->mispredicted()) { 1355 fetchRedirect[tid] = true; 1356 1357 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); |
1358 DPRINTF(IEW, "Predicted target was %#x.\n", inst->predPC); |
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1344#if ISA_HAS_DELAY_SLOT 1345 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n", 1346 inst->nextNPC); 1347#else 1348 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n", 1349 inst->nextPC); 1350#endif 1351 // If incorrect, then signal the ROB that it must be squashed. 1352 squashDueToBranch(inst, tid); 1353 | 1359#if ISA_HAS_DELAY_SLOT 1360 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n", 1361 inst->nextNPC); 1362#else 1363 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n", 1364 inst->nextPC); 1365#endif 1366 // If incorrect, then signal the ROB that it must be squashed. 1367 squashDueToBranch(inst, tid); 1368 |
1354 if (inst->predTaken()) { | 1369 if (inst->readPredTaken()) { |
1355 predictedTakenIncorrect++; 1356 } else { 1357 predictedNotTakenIncorrect++; 1358 } 1359 } else if (ldstQueue.violation(tid)) { 1360 // If there was an ordering violation, then get the 1361 // DynInst that caused the violation. Note that this 1362 // clears the violation signal. --- 104 unchanged lines hidden (view full) --- 1467 wroteToTimeBuffer = false; 1468 updatedQueues = false; 1469 1470 sortInsts(); 1471 1472 // Free function units marked as being freed this cycle. 1473 fuPool->processFreeUnits(); 1474 | 1370 predictedTakenIncorrect++; 1371 } else { 1372 predictedNotTakenIncorrect++; 1373 } 1374 } else if (ldstQueue.violation(tid)) { 1375 // If there was an ordering violation, then get the 1376 // DynInst that caused the violation. Note that this 1377 // clears the violation signal. --- 104 unchanged lines hidden (view full) --- 1482 wroteToTimeBuffer = false; 1483 updatedQueues = false; 1484 1485 sortInsts(); 1486 1487 // Free function units marked as being freed this cycle. 1488 fuPool->processFreeUnits(); 1489 |
1475 std::list<unsigned>::iterator threads = activeThreads->begin(); 1476 std::list<unsigned>::iterator end = activeThreads->end(); | 1490 std::list<unsigned>::iterator threads = (*activeThreads).begin(); |
1477 1478 // Check stall and squash signals, dispatch any instructions. | 1491 1492 // Check stall and squash signals, dispatch any instructions. |
1479 while (threads != end) { 1480 unsigned tid = *threads++; | 1493 while (threads != (*activeThreads).end()) { 1494 unsigned tid = *threads++; |
1481 1482 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 1483 1484 checkSignalsAndUpdate(tid); 1485 dispatch(tid); 1486 } 1487 1488 if (exeStatus != Squashing) { --- 23 unchanged lines hidden (view full) --- 1512 // Writeback any stores using any leftover bandwidth. 1513 ldstQueue.writebackStores(); 1514 1515 // Check the committed load/store signals to see if there's a load 1516 // or store to commit. Also check if it's being told to execute a 1517 // nonspeculative instruction. 1518 // This is pretty inefficient... 1519 | 1495 1496 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 1497 1498 checkSignalsAndUpdate(tid); 1499 dispatch(tid); 1500 } 1501 1502 if (exeStatus != Squashing) { --- 23 unchanged lines hidden (view full) --- 1526 // Writeback any stores using any leftover bandwidth. 1527 ldstQueue.writebackStores(); 1528 1529 // Check the committed load/store signals to see if there's a load 1530 // or store to commit. Also check if it's being told to execute a 1531 // nonspeculative instruction. 1532 // This is pretty inefficient... 1533 |
1520 threads = activeThreads->begin(); 1521 while (threads != end) { | 1534 threads = (*activeThreads).begin(); 1535 while (threads != (*activeThreads).end()) { |
1522 unsigned tid = (*threads++); 1523 1524 DPRINTF(IEW,"Processing [tid:%i]\n",tid); 1525 1526 // Update structures based on instructions committed. 1527 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 1528 !fromCommit->commitInfo[tid].squash && 1529 !fromCommit->commitInfo[tid].robSquashing) { --- 88 unchanged lines hidden --- | 1536 unsigned tid = (*threads++); 1537 1538 DPRINTF(IEW,"Processing [tid:%i]\n",tid); 1539 1540 // Update structures based on instructions committed. 1541 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 1542 !fromCommit->commitInfo[tid].squash && 1543 !fromCommit->commitInfo[tid].robSquashing) { --- 88 unchanged lines hidden --- |