iew_impl.hh (2702:8a3ee279559b) | iew_impl.hh (2727:91e17c7ee622) |
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1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 79 unchanged lines hidden (view full) --- 88 89template <class Impl> 90void 91DefaultIEW<Impl>::regStats() 92{ 93 using namespace Stats; 94 95 instQueue.regStats(); | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 79 unchanged lines hidden (view full) --- 88 89template <class Impl> 90void 91DefaultIEW<Impl>::regStats() 92{ 93 using namespace Stats; 94 95 instQueue.regStats(); |
96 ldstQueue.regStats(); |
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96 97 iewIdleCycles 98 .name(name() + ".iewIdleCycles") 99 .desc("Number of cycles IEW is idle"); 100 101 iewSquashCycles 102 .name(name() + ".iewSquashCycles") 103 .desc("Number of cycles IEW is squashing"); --- 29 unchanged lines hidden (view full) --- 133 iewIQFullEvents 134 .name(name() + ".iewIQFullEvents") 135 .desc("Number of times the IQ has become full, causing a stall"); 136 137 iewLSQFullEvents 138 .name(name() + ".iewLSQFullEvents") 139 .desc("Number of times the LSQ has become full, causing a stall"); 140 | 97 98 iewIdleCycles 99 .name(name() + ".iewIdleCycles") 100 .desc("Number of cycles IEW is idle"); 101 102 iewSquashCycles 103 .name(name() + ".iewSquashCycles") 104 .desc("Number of cycles IEW is squashing"); --- 29 unchanged lines hidden (view full) --- 134 iewIQFullEvents 135 .name(name() + ".iewIQFullEvents") 136 .desc("Number of times the IQ has become full, causing a stall"); 137 138 iewLSQFullEvents 139 .name(name() + ".iewLSQFullEvents") 140 .desc("Number of times the LSQ has become full, causing a stall"); 141 |
141 iewExecutedInsts 142 .name(name() + ".iewExecutedInsts") 143 .desc("Number of executed instructions"); 144 145 iewExecLoadInsts 146 .init(cpu->number_of_threads) 147 .name(name() + ".iewExecLoadInsts") 148 .desc("Number of load instructions executed") 149 .flags(total); 150 151 iewExecSquashedInsts 152 .name(name() + ".iewExecSquashedInsts") 153 .desc("Number of squashed instructions skipped in execute"); 154 | |
155 memOrderViolationEvents 156 .name(name() + ".memOrderViolationEvents") 157 .desc("Number of memory order violations"); 158 159 predictedTakenIncorrect 160 .name(name() + ".predictedTakenIncorrect") 161 .desc("Number of branches that were predicted taken incorrectly"); 162 163 predictedNotTakenIncorrect 164 .name(name() + ".predictedNotTakenIncorrect") 165 .desc("Number of branches that were predicted not taken incorrectly"); 166 167 branchMispredicts 168 .name(name() + ".branchMispredicts") 169 .desc("Number of branch mispredicts detected at execute"); 170 171 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 172 | 142 memOrderViolationEvents 143 .name(name() + ".memOrderViolationEvents") 144 .desc("Number of memory order violations"); 145 146 predictedTakenIncorrect 147 .name(name() + ".predictedTakenIncorrect") 148 .desc("Number of branches that were predicted taken incorrectly"); 149 150 predictedNotTakenIncorrect 151 .name(name() + ".predictedNotTakenIncorrect") 152 .desc("Number of branches that were predicted not taken incorrectly"); 153 154 branchMispredicts 155 .name(name() + ".branchMispredicts") 156 .desc("Number of branch mispredicts detected at execute"); 157 158 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 159 |
173 exeSwp | 160 iewExecutedInsts 161 .name(name() + ".EXEC:insts") 162 .desc("Number of executed instructions"); 163 164 iewExecLoadInsts |
174 .init(cpu->number_of_threads) | 165 .init(cpu->number_of_threads) |
166 .name(name() + ".EXEC:loads") 167 .desc("Number of load instructions executed") 168 .flags(total); 169 170 iewExecSquashedInsts 171 .name(name() + ".EXEC:squashedInsts") 172 .desc("Number of squashed instructions skipped in execute"); 173 174 iewExecutedSwp 175 .init(cpu->number_of_threads) |
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175 .name(name() + ".EXEC:swp") 176 .desc("number of swp insts executed") | 176 .name(name() + ".EXEC:swp") 177 .desc("number of swp insts executed") |
177 .flags(total) 178 ; | 178 .flags(total); |
179 | 179 |
180 exeNop | 180 iewExecutedNop |
181 .init(cpu->number_of_threads) 182 .name(name() + ".EXEC:nop") 183 .desc("number of nop insts executed") | 181 .init(cpu->number_of_threads) 182 .name(name() + ".EXEC:nop") 183 .desc("number of nop insts executed") |
184 .flags(total) 185 ; | 184 .flags(total); |
186 | 185 |
187 exeRefs | 186 iewExecutedRefs |
188 .init(cpu->number_of_threads) 189 .name(name() + ".EXEC:refs") 190 .desc("number of memory reference insts executed") | 187 .init(cpu->number_of_threads) 188 .name(name() + ".EXEC:refs") 189 .desc("number of memory reference insts executed") |
191 .flags(total) 192 ; | 190 .flags(total); |
193 | 191 |
194 exeBranches | 192 iewExecutedBranches |
195 .init(cpu->number_of_threads) 196 .name(name() + ".EXEC:branches") 197 .desc("Number of branches executed") | 193 .init(cpu->number_of_threads) 194 .name(name() + ".EXEC:branches") 195 .desc("Number of branches executed") |
198 .flags(total) 199 ; | 196 .flags(total); |
200 | 197 |
201 issueRate 202 .name(name() + ".EXEC:rate") 203 .desc("Inst execution rate") 204 .flags(total) 205 ; 206 issueRate = iewExecutedInsts / cpu->numCycles; 207 | |
208 iewExecStoreInsts 209 .name(name() + ".EXEC:stores") 210 .desc("Number of stores executed") | 198 iewExecStoreInsts 199 .name(name() + ".EXEC:stores") 200 .desc("Number of stores executed") |
211 .flags(total) 212 ; 213 iewExecStoreInsts = exeRefs - iewExecLoadInsts; 214/* 215 for (int i=0; i<Num_OpClasses; ++i) { 216 stringstream subname; 217 subname << opClassStrings[i] << "_delay"; 218 issue_delay_dist.subname(i, subname.str()); 219 } 220*/ 221 // 222 // Other stats 223 // | 201 .flags(total); 202 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; |
224 | 203 |
204 iewExecRate 205 .name(name() + ".EXEC:rate") 206 .desc("Inst execution rate") 207 .flags(total); 208 209 iewExecRate = iewExecutedInsts / cpu->numCycles; 210 |
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225 iewInstsToCommit 226 .init(cpu->number_of_threads) 227 .name(name() + ".WB:sent") 228 .desc("cumulative count of insts sent to commit") | 211 iewInstsToCommit 212 .init(cpu->number_of_threads) 213 .name(name() + ".WB:sent") 214 .desc("cumulative count of insts sent to commit") |
229 .flags(total) 230 ; | 215 .flags(total); |
231 232 writebackCount 233 .init(cpu->number_of_threads) 234 .name(name() + ".WB:count") 235 .desc("cumulative count of insts written-back") | 216 217 writebackCount 218 .init(cpu->number_of_threads) 219 .name(name() + ".WB:count") 220 .desc("cumulative count of insts written-back") |
236 .flags(total) 237 ; | 221 .flags(total); |
238 239 producerInst 240 .init(cpu->number_of_threads) 241 .name(name() + ".WB:producers") 242 .desc("num instructions producing a value") | 222 223 producerInst 224 .init(cpu->number_of_threads) 225 .name(name() + ".WB:producers") 226 .desc("num instructions producing a value") |
243 .flags(total) 244 ; | 227 .flags(total); |
245 246 consumerInst 247 .init(cpu->number_of_threads) 248 .name(name() + ".WB:consumers") 249 .desc("num instructions consuming a value") | 228 229 consumerInst 230 .init(cpu->number_of_threads) 231 .name(name() + ".WB:consumers") 232 .desc("num instructions consuming a value") |
250 .flags(total) 251 ; | 233 .flags(total); |
252 253 wbPenalized 254 .init(cpu->number_of_threads) 255 .name(name() + ".WB:penalized") 256 .desc("number of instrctions required to write to 'other' IQ") | 234 235 wbPenalized 236 .init(cpu->number_of_threads) 237 .name(name() + ".WB:penalized") 238 .desc("number of instrctions required to write to 'other' IQ") |
257 .flags(total) 258 ; | 239 .flags(total); |
259 260 wbPenalizedRate 261 .name(name() + ".WB:penalized_rate") 262 .desc ("fraction of instructions written-back that wrote to 'other' IQ") | 240 241 wbPenalizedRate 242 .name(name() + ".WB:penalized_rate") 243 .desc ("fraction of instructions written-back that wrote to 'other' IQ") |
263 .flags(total) 264 ; | 244 .flags(total); |
265 266 wbPenalizedRate = wbPenalized / writebackCount; 267 268 wbFanout 269 .name(name() + ".WB:fanout") 270 .desc("average fanout of values written-back") | 245 246 wbPenalizedRate = wbPenalized / writebackCount; 247 248 wbFanout 249 .name(name() + ".WB:fanout") 250 .desc("average fanout of values written-back") |
271 .flags(total) 272 ; | 251 .flags(total); |
273 274 wbFanout = producerInst / consumerInst; 275 276 wbRate 277 .name(name() + ".WB:rate") 278 .desc("insts written-back per cycle") | 252 253 wbFanout = producerInst / consumerInst; 254 255 wbRate 256 .name(name() + ".WB:rate") 257 .desc("insts written-back per cycle") |
279 .flags(total) 280 ; | 258 .flags(total); |
281 wbRate = writebackCount / cpu->numCycles; 282} 283 284template<class Impl> 285void 286DefaultIEW<Impl>::initStage() 287{ 288 for (int tid=0; tid < numThreads; tid++) { --- 804 unchanged lines hidden (view full) --- 1093 "skipping.\n", tid); 1094 1095 inst->setIssued(); 1096 inst->setExecuted(); 1097 inst->setCanCommit(); 1098 1099 instQueue.recordProducer(inst); 1100 | 259 wbRate = writebackCount / cpu->numCycles; 260} 261 262template<class Impl> 263void 264DefaultIEW<Impl>::initStage() 265{ 266 for (int tid=0; tid < numThreads; tid++) { --- 804 unchanged lines hidden (view full) --- 1071 "skipping.\n", tid); 1072 1073 inst->setIssued(); 1074 inst->setExecuted(); 1075 inst->setCanCommit(); 1076 1077 instQueue.recordProducer(inst); 1078 |
1101 exeNop[tid]++; | 1079 iewExecutedNop[tid]++; |
1102 1103 add_to_iq = false; 1104 } else if (inst->isExecuted()) { 1105 assert(0 && "Instruction shouldn't be executed.\n"); 1106 DPRINTF(IEW, "Issue: Executed branch encountered, " 1107 "skipping.\n"); 1108 1109 inst->setIssued(); --- 394 unchanged lines hidden (view full) --- 1504{ 1505 int thread_number = inst->threadNumber; 1506 1507 // 1508 // Pick off the software prefetches 1509 // 1510#ifdef TARGET_ALPHA 1511 if (inst->isDataPrefetch()) | 1080 1081 add_to_iq = false; 1082 } else if (inst->isExecuted()) { 1083 assert(0 && "Instruction shouldn't be executed.\n"); 1084 DPRINTF(IEW, "Issue: Executed branch encountered, " 1085 "skipping.\n"); 1086 1087 inst->setIssued(); --- 394 unchanged lines hidden (view full) --- 1482{ 1483 int thread_number = inst->threadNumber; 1484 1485 // 1486 // Pick off the software prefetches 1487 // 1488#ifdef TARGET_ALPHA 1489 if (inst->isDataPrefetch()) |
1512 exeSwp[thread_number]++; | 1490 iewExecutedSwp[thread_number]++; |
1513 else | 1491 else |
1514 iewExecutedInsts++; | 1492 iewIewExecutedcutedInsts++; |
1515#else 1516 iewExecutedInsts++; 1517#endif 1518 1519 // 1520 // Control operations 1521 // 1522 if (inst->isControl()) | 1493#else 1494 iewExecutedInsts++; 1495#endif 1496 1497 // 1498 // Control operations 1499 // 1500 if (inst->isControl()) |
1523 exeBranches[thread_number]++; | 1501 iewExecutedBranches[thread_number]++; |
1524 1525 // 1526 // Memory operations 1527 // 1528 if (inst->isMemRef()) { | 1502 1503 // 1504 // Memory operations 1505 // 1506 if (inst->isMemRef()) { |
1529 exeRefs[thread_number]++; | 1507 iewExecutedRefs[thread_number]++; |
1530 1531 if (inst->isLoad()) { 1532 iewExecLoadInsts[thread_number]++; 1533 } 1534 } 1535} | 1508 1509 if (inst->isLoad()) { 1510 iewExecLoadInsts[thread_number]++; 1511 } 1512 } 1513} |