iew_impl.hh (10231:cb2e6950956d) | iew_impl.hh (10239:592f0bb6bd6f) |
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1/* 2 * Copyright (c) 2010-2013 ARM Limited | 1/* 2 * Copyright (c) 2010-2013 ARM Limited |
3 * Copyright (c) 2013 Advanced Micro Devices, Inc. |
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3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 299 unchanged lines hidden (view full) --- 310DefaultIEW<Impl>::startupStage() 311{ 312 for (ThreadID tid = 0; tid < numThreads; tid++) { 313 toRename->iewInfo[tid].usedIQ = true; 314 toRename->iewInfo[tid].freeIQEntries = 315 instQueue.numFreeEntries(tid); 316 317 toRename->iewInfo[tid].usedLSQ = true; | 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated --- 299 unchanged lines hidden (view full) --- 311DefaultIEW<Impl>::startupStage() 312{ 313 for (ThreadID tid = 0; tid < numThreads; tid++) { 314 toRename->iewInfo[tid].usedIQ = true; 315 toRename->iewInfo[tid].freeIQEntries = 316 instQueue.numFreeEntries(tid); 317 318 toRename->iewInfo[tid].usedLSQ = true; |
318 toRename->iewInfo[tid].freeLSQEntries = 319 ldstQueue.numFreeEntries(tid); | 319 toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid); 320 toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid); |
320 } 321 322 // Initialize the checker's dcache port here 323 if (cpu->checker) { 324 cpu->checker->setDcachePort(&cpu->getDataPort()); 325 } 326 327 cpu->activateStage(O3CPU::IEWIdx); --- 134 unchanged lines hidden (view full) --- 462 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 463 updatedQueues = true; 464 465 // Clear the skid buffer in case it has any data in it. 466 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 467 tid, fromCommit->commitInfo[tid].doneSeqNum); 468 469 while (!skidBuffer[tid].empty()) { | 321 } 322 323 // Initialize the checker's dcache port here 324 if (cpu->checker) { 325 cpu->checker->setDcachePort(&cpu->getDataPort()); 326 } 327 328 cpu->activateStage(O3CPU::IEWIdx); --- 134 unchanged lines hidden (view full) --- 463 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 464 updatedQueues = true; 465 466 // Clear the skid buffer in case it has any data in it. 467 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 468 tid, fromCommit->commitInfo[tid].doneSeqNum); 469 470 while (!skidBuffer[tid].empty()) { |
470 if (skidBuffer[tid].front()->isLoad() || 471 skidBuffer[tid].front()->isStore() ) { 472 toRename->iewInfo[tid].dispatchedToLSQ++; | 471 if (skidBuffer[tid].front()->isLoad()) { 472 toRename->iewInfo[tid].dispatchedToLQ++; |
473 } | 473 } |
474 if (skidBuffer[tid].front()->isStore()) { 475 toRename->iewInfo[tid].dispatchedToSQ++; 476 } |
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474 475 toRename->iewInfo[tid].dispatched++; 476 477 skidBuffer[tid].pop(); 478 } 479 480 emptyRenameInsts(tid); 481} --- 416 unchanged lines hidden (view full) --- 898template <class Impl> 899void 900DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 901{ 902 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 903 904 while (!insts[tid].empty()) { 905 | 477 478 toRename->iewInfo[tid].dispatched++; 479 480 skidBuffer[tid].pop(); 481 } 482 483 emptyRenameInsts(tid); 484} --- 416 unchanged lines hidden (view full) --- 901template <class Impl> 902void 903DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 904{ 905 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 906 907 while (!insts[tid].empty()) { 908 |
906 if (insts[tid].front()->isLoad() || 907 insts[tid].front()->isStore() ) { 908 toRename->iewInfo[tid].dispatchedToLSQ++; | 909 if (insts[tid].front()->isLoad()) { 910 toRename->iewInfo[tid].dispatchedToLQ++; |
909 } | 911 } |
912 if (insts[tid].front()->isStore()) { 913 toRename->iewInfo[tid].dispatchedToSQ++; 914 } |
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910 911 toRename->iewInfo[tid].dispatched++; 912 913 insts[tid].pop(); 914 } 915} 916 917template <class Impl> --- 120 unchanged lines hidden (view full) --- 1038 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 1039 "not adding to IQ.\n", tid); 1040 1041 ++iewDispSquashedInsts; 1042 1043 insts_to_dispatch.pop(); 1044 1045 //Tell Rename That An Instruction has been processed | 915 916 toRename->iewInfo[tid].dispatched++; 917 918 insts[tid].pop(); 919 } 920} 921 922template <class Impl> --- 120 unchanged lines hidden (view full) --- 1043 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 1044 "not adding to IQ.\n", tid); 1045 1046 ++iewDispSquashedInsts; 1047 1048 insts_to_dispatch.pop(); 1049 1050 //Tell Rename That An Instruction has been processed |
1046 if (inst->isLoad() || inst->isStore()) { 1047 toRename->iewInfo[tid].dispatchedToLSQ++; | 1051 if (inst->isLoad()) { 1052 toRename->iewInfo[tid].dispatchedToLQ++; |
1048 } | 1053 } |
1054 if (inst->isStore()) { 1055 toRename->iewInfo[tid].dispatchedToSQ++; 1056 } 1057 |
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1049 toRename->iewInfo[tid].dispatched++; 1050 1051 continue; 1052 } 1053 1054 // Check for full conditions. 1055 if (instQueue.isFull(tid)) { 1056 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); --- 31 unchanged lines hidden (view full) --- 1088 // Reserve a spot in the load store queue for this 1089 // memory access. 1090 ldstQueue.insertLoad(inst); 1091 1092 ++iewDispLoadInsts; 1093 1094 add_to_iq = true; 1095 | 1058 toRename->iewInfo[tid].dispatched++; 1059 1060 continue; 1061 } 1062 1063 // Check for full conditions. 1064 if (instQueue.isFull(tid)) { 1065 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); --- 31 unchanged lines hidden (view full) --- 1097 // Reserve a spot in the load store queue for this 1098 // memory access. 1099 ldstQueue.insertLoad(inst); 1100 1101 ++iewDispLoadInsts; 1102 1103 add_to_iq = true; 1104 |
1096 toRename->iewInfo[tid].dispatchedToLSQ++; | 1105 toRename->iewInfo[tid].dispatchedToLQ++; |
1097 } else if (inst->isStore()) { 1098 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1099 "encountered, adding to LSQ.\n", tid); 1100 1101 ldstQueue.insertStore(inst); 1102 1103 ++iewDispStoreInsts; 1104 --- 6 unchanged lines hidden (view full) --- 1111 instQueue.insertNonSpec(inst); 1112 add_to_iq = false; 1113 1114 ++iewDispNonSpecInsts; 1115 } else { 1116 add_to_iq = true; 1117 } 1118 | 1106 } else if (inst->isStore()) { 1107 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1108 "encountered, adding to LSQ.\n", tid); 1109 1110 ldstQueue.insertStore(inst); 1111 1112 ++iewDispStoreInsts; 1113 --- 6 unchanged lines hidden (view full) --- 1120 instQueue.insertNonSpec(inst); 1121 add_to_iq = false; 1122 1123 ++iewDispNonSpecInsts; 1124 } else { 1125 add_to_iq = true; 1126 } 1127 |
1119 toRename->iewInfo[tid].dispatchedToLSQ++; | 1128 toRename->iewInfo[tid].dispatchedToSQ++; |
1120 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 1121 // Same as non-speculative stores. 1122 inst->setCanCommit(); 1123 instQueue.insertBarrier(inst); 1124 add_to_iq = false; 1125 } else if (inst->isNop()) { 1126 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 1127 "skipping.\n", tid); --- 480 unchanged lines hidden (view full) --- 1608 instQueue.getCount(tid); 1609 toFetch->iewInfo[tid].ldstqCount = 1610 ldstQueue.getCount(tid); 1611 1612 toRename->iewInfo[tid].usedIQ = true; 1613 toRename->iewInfo[tid].freeIQEntries = 1614 instQueue.numFreeEntries(tid); 1615 toRename->iewInfo[tid].usedLSQ = true; | 1129 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 1130 // Same as non-speculative stores. 1131 inst->setCanCommit(); 1132 instQueue.insertBarrier(inst); 1133 add_to_iq = false; 1134 } else if (inst->isNop()) { 1135 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 1136 "skipping.\n", tid); --- 480 unchanged lines hidden (view full) --- 1617 instQueue.getCount(tid); 1618 toFetch->iewInfo[tid].ldstqCount = 1619 ldstQueue.getCount(tid); 1620 1621 toRename->iewInfo[tid].usedIQ = true; 1622 toRename->iewInfo[tid].freeIQEntries = 1623 instQueue.numFreeEntries(tid); 1624 toRename->iewInfo[tid].usedLSQ = true; |
1616 toRename->iewInfo[tid].freeLSQEntries = 1617 ldstQueue.numFreeEntries(tid); | |
1618 | 1625 |
1626 toRename->iewInfo[tid].freeLQEntries = 1627 ldstQueue.numFreeLoadEntries(tid); 1628 toRename->iewInfo[tid].freeSQEntries = 1629 ldstQueue.numFreeStoreEntries(tid); 1630 |
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1619 wroteToTimeBuffer = true; 1620 } 1621 1622 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 1623 tid, toRename->iewInfo[tid].dispatched); 1624 } 1625 1626 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " | 1631 wroteToTimeBuffer = true; 1632 } 1633 1634 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 1635 tid, toRename->iewInfo[tid].dispatched); 1636 } 1637 1638 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " |
1627 "LSQ has %i free entries.\n", | 1639 "LQ has %i free entries. SQ has %i free entries.\n", |
1628 instQueue.numFreeEntries(), instQueue.hasReadyInsts(), | 1640 instQueue.numFreeEntries(), instQueue.hasReadyInsts(), |
1629 ldstQueue.numFreeEntries()); | 1641 ldstQueue.numFreeLoadEntries(), ldstQueue.numFreeStoreEntries()); |
1630 1631 updateStatus(); 1632 1633 if (wroteToTimeBuffer) { 1634 DPRINTF(Activity, "Activity this cycle.\n"); 1635 cpu->activityThisCycle(); 1636 } 1637} --- 65 unchanged lines hidden --- | 1642 1643 updateStatus(); 1644 1645 if (wroteToTimeBuffer) { 1646 DPRINTF(Activity, "Activity this cycle.\n"); 1647 cpu->activityThisCycle(); 1648 } 1649} --- 65 unchanged lines hidden --- |