1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_O3_IEW_IMPL_IMPL_HH__
45#define __CPU_O3_IEW_IMPL_IMPL_HH__
46
47// @todo: Fix the instantaneous communication among all the stages within
48// iew. There's a clear delay between issue and execute, yet backwards
49// communication happens simultaneously.
50
51#include <queue>
52
53#include "arch/utility.hh"
54#include "config/the_isa.hh"
55#include "cpu/checker/cpu.hh"
56#include "cpu/o3/fu_pool.hh"
57#include "cpu/o3/iew.hh"
58#include "cpu/timebuf.hh"
59#include "debug/Activity.hh"
60#include "debug/Drain.hh"
61#include "debug/IEW.hh"
62#include "debug/O3PipeView.hh"
63#include "params/DerivO3CPU.hh"
64
65using namespace std;
66
67template<class Impl>
68DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
69 : issueToExecQueue(params->backComSize, params->forwardComSize),
70 cpu(_cpu),
71 instQueue(_cpu, this, params),
72 ldstQueue(_cpu, this, params),
73 fuPool(params->fuPool),
74 commitToIEWDelay(params->commitToIEWDelay),
75 renameToIEWDelay(params->renameToIEWDelay),
76 issueToExecuteDelay(params->issueToExecuteDelay),
77 dispatchWidth(params->dispatchWidth),
78 issueWidth(params->issueWidth),
79 wbWidth(params->wbWidth),
80 numThreads(params->numThreads)
81{
82 if (dispatchWidth > Impl::MaxWidth)
83 fatal("dispatchWidth (%d) is larger than compiled limit (%d),\n"
84 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
85 dispatchWidth, static_cast<int>(Impl::MaxWidth));
86 if (issueWidth > Impl::MaxWidth)
87 fatal("issueWidth (%d) is larger than compiled limit (%d),\n"
88 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
89 issueWidth, static_cast<int>(Impl::MaxWidth));
90 if (wbWidth > Impl::MaxWidth)
91 fatal("wbWidth (%d) is larger than compiled limit (%d),\n"
92 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
93 wbWidth, static_cast<int>(Impl::MaxWidth));
94
95 _status = Active;
96 exeStatus = Running;
97 wbStatus = Idle;
98
99 // Setup wire to read instructions coming from issue.
100 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
101
102 // Instruction queue needs the queue between issue and execute.
103 instQueue.setIssueToExecuteQueue(&issueToExecQueue);
104
105 for (ThreadID tid = 0; tid < numThreads; tid++) {
106 dispatchStatus[tid] = Running;
107 fetchRedirect[tid] = false;
108 }
109
110 updateLSQNextCycle = false;
111
112 skidBufferMax = (renameToIEWDelay + 1) * params->renameWidth;
113}
114
115template <class Impl>
116std::string
117DefaultIEW<Impl>::name() const
118{
119 return cpu->name() + ".iew";
120}
121
122template <class Impl>
123void
124DefaultIEW<Impl>::regProbePoints()
125{
126 ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch");
127 ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict");
128 /**
129 * Probe point with dynamic instruction as the argument used to probe when
130 * an instruction starts to execute.
131 */
132 ppExecute = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(),
133 "Execute");
134 /**
135 * Probe point with dynamic instruction as the argument used to probe when
136 * an instruction execution completes and it is marked ready to commit.
137 */
138 ppToCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(),
139 "ToCommit");
140}
141
142template <class Impl>
143void
144DefaultIEW<Impl>::regStats()
145{
146 using namespace Stats;
147
148 instQueue.regStats();
149 ldstQueue.regStats();
150
151 iewIdleCycles
152 .name(name() + ".iewIdleCycles")
153 .desc("Number of cycles IEW is idle");
154
155 iewSquashCycles
156 .name(name() + ".iewSquashCycles")
157 .desc("Number of cycles IEW is squashing");
158
159 iewBlockCycles
160 .name(name() + ".iewBlockCycles")
161 .desc("Number of cycles IEW is blocking");
162
163 iewUnblockCycles
164 .name(name() + ".iewUnblockCycles")
165 .desc("Number of cycles IEW is unblocking");
166
167 iewDispatchedInsts
168 .name(name() + ".iewDispatchedInsts")
169 .desc("Number of instructions dispatched to IQ");
170
171 iewDispSquashedInsts
172 .name(name() + ".iewDispSquashedInsts")
173 .desc("Number of squashed instructions skipped by dispatch");
174
175 iewDispLoadInsts
176 .name(name() + ".iewDispLoadInsts")
177 .desc("Number of dispatched load instructions");
178
179 iewDispStoreInsts
180 .name(name() + ".iewDispStoreInsts")
181 .desc("Number of dispatched store instructions");
182
183 iewDispNonSpecInsts
184 .name(name() + ".iewDispNonSpecInsts")
185 .desc("Number of dispatched non-speculative instructions");
186
187 iewIQFullEvents
188 .name(name() + ".iewIQFullEvents")
189 .desc("Number of times the IQ has become full, causing a stall");
190
191 iewLSQFullEvents
192 .name(name() + ".iewLSQFullEvents")
193 .desc("Number of times the LSQ has become full, causing a stall");
194
195 memOrderViolationEvents
196 .name(name() + ".memOrderViolationEvents")
197 .desc("Number of memory order violations");
198
199 predictedTakenIncorrect
200 .name(name() + ".predictedTakenIncorrect")
201 .desc("Number of branches that were predicted taken incorrectly");
202
203 predictedNotTakenIncorrect
204 .name(name() + ".predictedNotTakenIncorrect")
205 .desc("Number of branches that were predicted not taken incorrectly");
206
207 branchMispredicts
208 .name(name() + ".branchMispredicts")
209 .desc("Number of branch mispredicts detected at execute");
210
211 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
212
213 iewExecutedInsts
214 .name(name() + ".iewExecutedInsts")
215 .desc("Number of executed instructions");
216
217 iewExecLoadInsts
218 .init(cpu->numThreads)
219 .name(name() + ".iewExecLoadInsts")
220 .desc("Number of load instructions executed")
221 .flags(total);
222
223 iewExecSquashedInsts
224 .name(name() + ".iewExecSquashedInsts")
225 .desc("Number of squashed instructions skipped in execute");
226
227 iewExecutedSwp
228 .init(cpu->numThreads)
229 .name(name() + ".exec_swp")
230 .desc("number of swp insts executed")
231 .flags(total);
232
233 iewExecutedNop
234 .init(cpu->numThreads)
235 .name(name() + ".exec_nop")
236 .desc("number of nop insts executed")
237 .flags(total);
238
239 iewExecutedRefs
240 .init(cpu->numThreads)
241 .name(name() + ".exec_refs")
242 .desc("number of memory reference insts executed")
243 .flags(total);
244
245 iewExecutedBranches
246 .init(cpu->numThreads)
247 .name(name() + ".exec_branches")
248 .desc("Number of branches executed")
249 .flags(total);
250
251 iewExecStoreInsts
252 .name(name() + ".exec_stores")
253 .desc("Number of stores executed")
254 .flags(total);
255 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
256
257 iewExecRate
258 .name(name() + ".exec_rate")
259 .desc("Inst execution rate")
260 .flags(total);
261
262 iewExecRate = iewExecutedInsts / cpu->numCycles;
263
264 iewInstsToCommit
265 .init(cpu->numThreads)
266 .name(name() + ".wb_sent")
267 .desc("cumulative count of insts sent to commit")
268 .flags(total);
269
270 writebackCount
271 .init(cpu->numThreads)
272 .name(name() + ".wb_count")
273 .desc("cumulative count of insts written-back")
274 .flags(total);
275
276 producerInst
277 .init(cpu->numThreads)
278 .name(name() + ".wb_producers")
279 .desc("num instructions producing a value")
280 .flags(total);
281
282 consumerInst
283 .init(cpu->numThreads)
284 .name(name() + ".wb_consumers")
285 .desc("num instructions consuming a value")
286 .flags(total);
287
288 wbFanout
289 .name(name() + ".wb_fanout")
290 .desc("average fanout of values written-back")
291 .flags(total);
292
293 wbFanout = producerInst / consumerInst;
294
295 wbRate
296 .name(name() + ".wb_rate")
297 .desc("insts written-back per cycle")
298 .flags(total);
299 wbRate = writebackCount / cpu->numCycles;
300}
301
302template<class Impl>
303void
304DefaultIEW<Impl>::startupStage()
305{
306 for (ThreadID tid = 0; tid < numThreads; tid++) {
307 toRename->iewInfo[tid].usedIQ = true;
308 toRename->iewInfo[tid].freeIQEntries =
309 instQueue.numFreeEntries(tid);
310
311 toRename->iewInfo[tid].usedLSQ = true;
312 toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid);
313 toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid);
314 }
315
316 // Initialize the checker's dcache port here
317 if (cpu->checker) {
318 cpu->checker->setDcachePort(&cpu->getDataPort());
319 }
320
321 cpu->activateStage(O3CPU::IEWIdx);
322}
323
324template<class Impl>
325void
326DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
327{
328 timeBuffer = tb_ptr;
329
330 // Setup wire to read information from time buffer, from commit.
331 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
332
333 // Setup wire to write information back to previous stages.
334 toRename = timeBuffer->getWire(0);
335
336 toFetch = timeBuffer->getWire(0);
337
338 // Instruction queue also needs main time buffer.
339 instQueue.setTimeBuffer(tb_ptr);
340}
341
342template<class Impl>
343void
344DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
345{
346 renameQueue = rq_ptr;
347
348 // Setup wire to read information from rename queue.
349 fromRename = renameQueue->getWire(-renameToIEWDelay);
350}
351
352template<class Impl>
353void
354DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
355{
356 iewQueue = iq_ptr;
357
358 // Setup wire to write instructions to commit.
359 toCommit = iewQueue->getWire(0);
360}
361
362template<class Impl>
363void
364DefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
365{
366 activeThreads = at_ptr;
367
368 ldstQueue.setActiveThreads(at_ptr);
369 instQueue.setActiveThreads(at_ptr);
370}
371
372template<class Impl>
373void
374DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
375{
376 scoreboard = sb_ptr;
377}
378
379template <class Impl>
380bool
381DefaultIEW<Impl>::isDrained() const
382{
383 bool drained = ldstQueue.isDrained() && instQueue.isDrained();
384
385 for (ThreadID tid = 0; tid < numThreads; tid++) {
386 if (!insts[tid].empty()) {
387 DPRINTF(Drain, "%i: Insts not empty.\n", tid);
388 drained = false;
389 }
390 if (!skidBuffer[tid].empty()) {
391 DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid);
392 drained = false;
393 }
394 }
395
396 // Also check the FU pool as instructions are "stored" in FU
397 // completion events until they are done and not accounted for
398 // above
399 if (drained && !fuPool->isDrained()) {
400 DPRINTF(Drain, "FU pool still busy.\n");
401 drained = false;
402 }
403
404 return drained;
405}
406
407template <class Impl>
408void
409DefaultIEW<Impl>::drainSanityCheck() const
410{
411 assert(isDrained());
412
413 instQueue.drainSanityCheck();
414 ldstQueue.drainSanityCheck();
415}
416
417template <class Impl>
418void
419DefaultIEW<Impl>::takeOverFrom()
420{
421 // Reset all state.
422 _status = Active;
423 exeStatus = Running;
424 wbStatus = Idle;
425
426 instQueue.takeOverFrom();
427 ldstQueue.takeOverFrom();
428 fuPool->takeOverFrom();
429
430 startupStage();
431 cpu->activityThisCycle();
432
433 for (ThreadID tid = 0; tid < numThreads; tid++) {
434 dispatchStatus[tid] = Running;
435 fetchRedirect[tid] = false;
436 }
437
438 updateLSQNextCycle = false;
439
440 for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
441 issueToExecQueue.advance();
442 }
443}
444
445template<class Impl>
446void
447DefaultIEW<Impl>::squash(ThreadID tid)
448{
449 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid);
450
451 // Tell the IQ to start squashing.
452 instQueue.squash(tid);
453
454 // Tell the LDSTQ to start squashing.
455 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
456 updatedQueues = true;
457
458 // Clear the skid buffer in case it has any data in it.
459 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
460 tid, fromCommit->commitInfo[tid].doneSeqNum);
461
462 while (!skidBuffer[tid].empty()) {
463 if (skidBuffer[tid].front()->isLoad()) {
464 toRename->iewInfo[tid].dispatchedToLQ++;
465 }
466 if (skidBuffer[tid].front()->isStore()) {
467 toRename->iewInfo[tid].dispatchedToSQ++;
468 }
469
470 toRename->iewInfo[tid].dispatched++;
471
472 skidBuffer[tid].pop();
473 }
474
475 emptyRenameInsts(tid);
476}
477
478template<class Impl>
479void
480DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
481{
482 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
483 "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
484
485 if (!toCommit->squash[tid] ||
486 inst->seqNum < toCommit->squashedSeqNum[tid]) {
487 toCommit->squash[tid] = true;
488 toCommit->squashedSeqNum[tid] = inst->seqNum;
489 toCommit->branchTaken[tid] = inst->pcState().branching();
490
491 TheISA::PCState pc = inst->pcState();
492 TheISA::advancePC(pc, inst->staticInst);
493
494 toCommit->pc[tid] = pc;
495 toCommit->mispredictInst[tid] = inst;
496 toCommit->includeSquashInst[tid] = false;
497
498 wroteToTimeBuffer = true;
499 }
500
501}
502
503template<class Impl>
504void
505DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
506{
507 DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger "
508 "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
509 // Need to include inst->seqNum in the following comparison to cover the
510 // corner case when a branch misprediction and a memory violation for the
511 // same instruction (e.g. load PC) are detected in the same cycle. In this
512 // case the memory violator should take precedence over the branch
513 // misprediction because it requires the violator itself to be included in
514 // the squash.
515 if (!toCommit->squash[tid] ||
516 inst->seqNum <= toCommit->squashedSeqNum[tid]) {
517 toCommit->squash[tid] = true;
518
519 toCommit->squashedSeqNum[tid] = inst->seqNum;
520 toCommit->pc[tid] = inst->pcState();
521 toCommit->mispredictInst[tid] = NULL;
522
523 // Must include the memory violator in the squash.
524 toCommit->includeSquashInst[tid] = true;
525
526 wroteToTimeBuffer = true;
527 }
528}
529
530template<class Impl>
531void
532DefaultIEW<Impl>::block(ThreadID tid)
533{
534 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
535
536 if (dispatchStatus[tid] != Blocked &&
537 dispatchStatus[tid] != Unblocking) {
538 toRename->iewBlock[tid] = true;
539 wroteToTimeBuffer = true;
540 }
541
542 // Add the current inputs to the skid buffer so they can be
543 // reprocessed when this stage unblocks.
544 skidInsert(tid);
545
546 dispatchStatus[tid] = Blocked;
547}
548
549template<class Impl>
550void
551DefaultIEW<Impl>::unblock(ThreadID tid)
552{
553 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
554 "buffer %u.\n",tid, tid);
555
556 // If the skid bufffer is empty, signal back to previous stages to unblock.
557 // Also switch status to running.
558 if (skidBuffer[tid].empty()) {
559 toRename->iewUnblock[tid] = true;
560 wroteToTimeBuffer = true;
561 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
562 dispatchStatus[tid] = Running;
563 }
564}
565
566template<class Impl>
567void
568DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
569{
570 instQueue.wakeDependents(inst);
571}
572
573template<class Impl>
574void
575DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
576{
577 instQueue.rescheduleMemInst(inst);
578}
579
580template<class Impl>
581void
582DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
583{
584 instQueue.replayMemInst(inst);
585}
586
587template<class Impl>
588void
589DefaultIEW<Impl>::blockMemInst(DynInstPtr& inst)
590{
591 instQueue.blockMemInst(inst);
592}
593
594template<class Impl>
595void
596DefaultIEW<Impl>::cacheUnblocked()
597{
598 instQueue.cacheUnblocked();
599}
600
601template<class Impl>
602void
603DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
604{
605 // This function should not be called after writebackInsts in a
606 // single cycle. That will cause problems with an instruction
607 // being added to the queue to commit without being processed by
608 // writebackInsts prior to being sent to commit.
609
610 // First check the time slot that this instruction will write
611 // to. If there are free write ports at the time, then go ahead
612 // and write the instruction to that time. If there are not,
613 // keep looking back to see where's the first time there's a
614 // free slot.
615 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
616 ++wbNumInst;
617 if (wbNumInst == wbWidth) {
618 ++wbCycle;
619 wbNumInst = 0;
620 }
621 }
622
623 DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
624 wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
625 // Add finished instruction to queue to commit.
626 (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
627 (*iewQueue)[wbCycle].size++;
628}
629
630template <class Impl>
631unsigned
632DefaultIEW<Impl>::validInstsFromRename()
633{
634 unsigned inst_count = 0;
635
636 for (int i=0; i<fromRename->size; i++) {
637 if (!fromRename->insts[i]->isSquashed())
638 inst_count++;
639 }
640
641 return inst_count;
642}
643
644template<class Impl>
645void
646DefaultIEW<Impl>::skidInsert(ThreadID tid)
647{
648 DynInstPtr inst = NULL;
649
650 while (!insts[tid].empty()) {
651 inst = insts[tid].front();
652
653 insts[tid].pop();
654
655 DPRINTF(IEW,"[tid:%i]: Inserting [sn:%lli] PC:%s into "
656 "dispatch skidBuffer %i\n",tid, inst->seqNum,
657 inst->pcState(),tid);
658
659 skidBuffer[tid].push(inst);
660 }
661
662 assert(skidBuffer[tid].size() <= skidBufferMax &&
663 "Skidbuffer Exceeded Max Size");
664}
665
666template<class Impl>
667int
668DefaultIEW<Impl>::skidCount()
669{
670 int max=0;
671
672 list<ThreadID>::iterator threads = activeThreads->begin();
673 list<ThreadID>::iterator end = activeThreads->end();
674
675 while (threads != end) {
676 ThreadID tid = *threads++;
677 unsigned thread_count = skidBuffer[tid].size();
678 if (max < thread_count)
679 max = thread_count;
680 }
681
682 return max;
683}
684
685template<class Impl>
686bool
687DefaultIEW<Impl>::skidsEmpty()
688{
689 list<ThreadID>::iterator threads = activeThreads->begin();
690 list<ThreadID>::iterator end = activeThreads->end();
691
692 while (threads != end) {
693 ThreadID tid = *threads++;
694
695 if (!skidBuffer[tid].empty())
696 return false;
697 }
698
699 return true;
700}
701
702template <class Impl>
703void
704DefaultIEW<Impl>::updateStatus()
705{
706 bool any_unblocking = false;
707
708 list<ThreadID>::iterator threads = activeThreads->begin();
709 list<ThreadID>::iterator end = activeThreads->end();
710
711 while (threads != end) {
712 ThreadID tid = *threads++;
713
714 if (dispatchStatus[tid] == Unblocking) {
715 any_unblocking = true;
716 break;
717 }
718 }
719
720 // If there are no ready instructions waiting to be scheduled by the IQ,
721 // and there's no stores waiting to write back, and dispatch is not
722 // unblocking, then there is no internal activity for the IEW stage.
723 instQueue.intInstQueueReads++;
724 if (_status == Active && !instQueue.hasReadyInsts() &&
725 !ldstQueue.willWB() && !any_unblocking) {
726 DPRINTF(IEW, "IEW switching to idle\n");
727
728 deactivateStage();
729
730 _status = Inactive;
731 } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
732 ldstQueue.willWB() ||
733 any_unblocking)) {
734 // Otherwise there is internal activity. Set to active.
735 DPRINTF(IEW, "IEW switching to active\n");
736
737 activateStage();
738
739 _status = Active;
740 }
741}
742
743template <class Impl>
744void
745DefaultIEW<Impl>::resetEntries()
746{
747 instQueue.resetEntries();
748 ldstQueue.resetEntries();
749}
750
751template <class Impl>
752bool
753DefaultIEW<Impl>::checkStall(ThreadID tid)
754{
755 bool ret_val(false);
756
757 if (fromCommit->commitInfo[tid].robSquashing) {
758 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
759 ret_val = true;
760 } else if (instQueue.isFull(tid)) {
761 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid);
762 ret_val = true;
763 }
764
765 return ret_val;
766}
767
768template <class Impl>
769void
770DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
771{
772 // Check if there's a squash signal, squash if there is
773 // Check stall signals, block if there is.
774 // If status was Blocked
775 // if so then go to unblocking
776 // If status was Squashing
777 // check if squashing is not high. Switch to running this cycle.
778
779 if (fromCommit->commitInfo[tid].squash) {
780 squash(tid);
781
782 if (dispatchStatus[tid] == Blocked ||
783 dispatchStatus[tid] == Unblocking) {
784 toRename->iewUnblock[tid] = true;
785 wroteToTimeBuffer = true;
786 }
787
788 dispatchStatus[tid] = Squashing;
789 fetchRedirect[tid] = false;
790 return;
791 }
792
793 if (fromCommit->commitInfo[tid].robSquashing) {
794 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
795
796 dispatchStatus[tid] = Squashing;
797 emptyRenameInsts(tid);
798 wroteToTimeBuffer = true;
799 }
800
801 if (checkStall(tid)) {
802 block(tid);
803 dispatchStatus[tid] = Blocked;
804 return;
805 }
806
807 if (dispatchStatus[tid] == Blocked) {
808 // Status from previous cycle was blocked, but there are no more stall
809 // conditions. Switch over to unblocking.
810 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
811 tid);
812
813 dispatchStatus[tid] = Unblocking;
814
815 unblock(tid);
816
817 return;
818 }
819
820 if (dispatchStatus[tid] == Squashing) {
821 // Switch status to running if rename isn't being told to block or
822 // squash this cycle.
823 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
824 tid);
825
826 dispatchStatus[tid] = Running;
827
828 return;
829 }
830}
831
832template <class Impl>
833void
834DefaultIEW<Impl>::sortInsts()
835{
836 int insts_from_rename = fromRename->size;
837#ifdef DEBUG
838 for (ThreadID tid = 0; tid < numThreads; tid++)
839 assert(insts[tid].empty());
840#endif
841 for (int i = 0; i < insts_from_rename; ++i) {
842 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
843 }
844}
845
846template <class Impl>
847void
848DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid)
849{
850 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
851
852 while (!insts[tid].empty()) {
853
854 if (insts[tid].front()->isLoad()) {
855 toRename->iewInfo[tid].dispatchedToLQ++;
856 }
857 if (insts[tid].front()->isStore()) {
858 toRename->iewInfo[tid].dispatchedToSQ++;
859 }
860
861 toRename->iewInfo[tid].dispatched++;
862
863 insts[tid].pop();
864 }
865}
866
867template <class Impl>
868void
869DefaultIEW<Impl>::wakeCPU()
870{
871 cpu->wakeCPU();
872}
873
874template <class Impl>
875void
876DefaultIEW<Impl>::activityThisCycle()
877{
878 DPRINTF(Activity, "Activity this cycle.\n");
879 cpu->activityThisCycle();
880}
881
882template <class Impl>
883inline void
884DefaultIEW<Impl>::activateStage()
885{
886 DPRINTF(Activity, "Activating stage.\n");
887 cpu->activateStage(O3CPU::IEWIdx);
888}
889
890template <class Impl>
891inline void
892DefaultIEW<Impl>::deactivateStage()
893{
894 DPRINTF(Activity, "Deactivating stage.\n");
895 cpu->deactivateStage(O3CPU::IEWIdx);
896}
897
898template<class Impl>
899void
900DefaultIEW<Impl>::dispatch(ThreadID tid)
901{
902 // If status is Running or idle,
903 // call dispatchInsts()
904 // If status is Unblocking,
905 // buffer any instructions coming from rename
906 // continue trying to empty skid buffer
907 // check if stall conditions have passed
908
909 if (dispatchStatus[tid] == Blocked) {
910 ++iewBlockCycles;
911
912 } else if (dispatchStatus[tid] == Squashing) {
913 ++iewSquashCycles;
914 }
915
916 // Dispatch should try to dispatch as many instructions as its bandwidth
917 // will allow, as long as it is not currently blocked.
918 if (dispatchStatus[tid] == Running ||
919 dispatchStatus[tid] == Idle) {
920 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
921 "dispatch.\n", tid);
922
923 dispatchInsts(tid);
924 } else if (dispatchStatus[tid] == Unblocking) {
925 // Make sure that the skid buffer has something in it if the
926 // status is unblocking.
927 assert(!skidsEmpty());
928
929 // If the status was unblocking, then instructions from the skid
930 // buffer were used. Remove those instructions and handle
931 // the rest of unblocking.
932 dispatchInsts(tid);
933
934 ++iewUnblockCycles;
935
936 if (validInstsFromRename()) {
937 // Add the current inputs to the skid buffer so they can be
938 // reprocessed when this stage unblocks.
939 skidInsert(tid);
940 }
941
942 unblock(tid);
943 }
944}
945
946template <class Impl>
947void
948DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
949{
950 // Obtain instructions from skid buffer if unblocking, or queue from rename
951 // otherwise.
952 std::queue<DynInstPtr> &insts_to_dispatch =
953 dispatchStatus[tid] == Unblocking ?
954 skidBuffer[tid] : insts[tid];
955
956 int insts_to_add = insts_to_dispatch.size();
957
958 DynInstPtr inst;
959 bool add_to_iq = false;
960 int dis_num_inst = 0;
961
962 // Loop through the instructions, putting them in the instruction
963 // queue.
964 for ( ; dis_num_inst < insts_to_add &&
965 dis_num_inst < dispatchWidth;
966 ++dis_num_inst)
967 {
968 inst = insts_to_dispatch.front();
969
970 if (dispatchStatus[tid] == Unblocking) {
971 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
972 "buffer\n", tid);
973 }
974
975 // Make sure there's a valid instruction there.
976 assert(inst);
977
978 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to "
979 "IQ.\n",
980 tid, inst->pcState(), inst->seqNum, inst->threadNumber);
981
982 // Be sure to mark these instructions as ready so that the
983 // commit stage can go ahead and execute them, and mark
984 // them as issued so the IQ doesn't reprocess them.
985
986 // Check for squashed instructions.
987 if (inst->isSquashed()) {
988 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
989 "not adding to IQ.\n", tid);
990
991 ++iewDispSquashedInsts;
992
993 insts_to_dispatch.pop();
994
995 //Tell Rename That An Instruction has been processed
996 if (inst->isLoad()) {
997 toRename->iewInfo[tid].dispatchedToLQ++;
998 }
999 if (inst->isStore()) {
1000 toRename->iewInfo[tid].dispatchedToSQ++;
1001 }
1002
1003 toRename->iewInfo[tid].dispatched++;
1004
1005 continue;
1006 }
1007
1008 // Check for full conditions.
1009 if (instQueue.isFull(tid)) {
1010 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1011
1012 // Call function to start blocking.
1013 block(tid);
1014
1015 // Set unblock to false. Special case where we are using
1016 // skidbuffer (unblocking) instructions but then we still
1017 // get full in the IQ.
1018 toRename->iewUnblock[tid] = false;
1019
1020 ++iewIQFullEvents;
1021 break;
1022 }
1023
1024 // Check LSQ if inst is LD/ST
1025 if ((inst->isLoad() && ldstQueue.lqFull(tid)) ||
1026 (inst->isStore() && ldstQueue.sqFull(tid))) {
1027 DPRINTF(IEW, "[tid:%i]: Issue: %s has become full.\n",tid,
1028 inst->isLoad() ? "LQ" : "SQ");
1029
1030 // Call function to start blocking.
1031 block(tid);
1032
1033 // Set unblock to false. Special case where we are using
1034 // skidbuffer (unblocking) instructions but then we still
1035 // get full in the IQ.
1036 toRename->iewUnblock[tid] = false;
1037
1038 ++iewLSQFullEvents;
1039 break;
1040 }
1041
1042 // Otherwise issue the instruction just fine.
1043 if (inst->isLoad()) {
1044 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1045 "encountered, adding to LSQ.\n", tid);
1046
1047 // Reserve a spot in the load store queue for this
1048 // memory access.
1049 ldstQueue.insertLoad(inst);
1050
1051 ++iewDispLoadInsts;
1052
1053 add_to_iq = true;
1054
1055 toRename->iewInfo[tid].dispatchedToLQ++;
1056 } else if (inst->isStore()) {
1057 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1058 "encountered, adding to LSQ.\n", tid);
1059
1060 ldstQueue.insertStore(inst);
1061
1062 ++iewDispStoreInsts;
1063
1064 if (inst->isStoreConditional()) {
1065 // Store conditionals need to be set as "canCommit()"
1066 // so that commit can process them when they reach the
1067 // head of commit.
1068 // @todo: This is somewhat specific to Alpha.
1069 inst->setCanCommit();
1070 instQueue.insertNonSpec(inst);
1071 add_to_iq = false;
1072
1073 ++iewDispNonSpecInsts;
1074 } else {
1075 add_to_iq = true;
1076 }
1077
1078 toRename->iewInfo[tid].dispatchedToSQ++;
1079 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1080 // Same as non-speculative stores.
1081 inst->setCanCommit();
1082 instQueue.insertBarrier(inst);
1083 add_to_iq = false;
1084 } else if (inst->isNop()) {
1085 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1086 "skipping.\n", tid);
1087
1088 inst->setIssued();
1089 inst->setExecuted();
1090 inst->setCanCommit();
1091
1092 instQueue.recordProducer(inst);
1093
1094 iewExecutedNop[tid]++;
1095
1096 add_to_iq = false;
1097 } else {
1098 assert(!inst->isExecuted());
1099 add_to_iq = true;
1100 }
1101
1102 if (inst->isNonSpeculative()) {
1103 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1104 "encountered, skipping.\n", tid);
1105
1106 // Same as non-speculative stores.
1107 inst->setCanCommit();
1108
1109 // Specifically insert it as nonspeculative.
1110 instQueue.insertNonSpec(inst);
1111
1112 ++iewDispNonSpecInsts;
1113
1114 add_to_iq = false;
1115 }
1116
1117 // If the instruction queue is not full, then add the
1118 // instruction.
1119 if (add_to_iq) {
1120 instQueue.insert(inst);
1121 }
1122
1123 insts_to_dispatch.pop();
1124
1125 toRename->iewInfo[tid].dispatched++;
1126
1127 ++iewDispatchedInsts;
1128
1129#if TRACING_ON
1130 inst->dispatchTick = curTick() - inst->fetchTick;
1131#endif
1132 ppDispatch->notify(inst);
1133 }
1134
1135 if (!insts_to_dispatch.empty()) {
1136 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1137 block(tid);
1138 toRename->iewUnblock[tid] = false;
1139 }
1140
1141 if (dispatchStatus[tid] == Idle && dis_num_inst) {
1142 dispatchStatus[tid] = Running;
1143
1144 updatedQueues = true;
1145 }
1146
1147 dis_num_inst = 0;
1148}
1149
1150template <class Impl>
1151void
1152DefaultIEW<Impl>::printAvailableInsts()
1153{
1154 int inst = 0;
1155
1156 std::cout << "Available Instructions: ";
1157
1158 while (fromIssue->insts[inst]) {
1159
1160 if (inst%3==0) std::cout << "\n\t";
1161
1162 std::cout << "PC: " << fromIssue->insts[inst]->pcState()
1163 << " TN: " << fromIssue->insts[inst]->threadNumber
1164 << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1165
1166 inst++;
1167
1168 }
1169
1170 std::cout << "\n";
1171}
1172
1173template <class Impl>
1174void
1175DefaultIEW<Impl>::executeInsts()
1176{
1177 wbNumInst = 0;
1178 wbCycle = 0;
1179
1180 list<ThreadID>::iterator threads = activeThreads->begin();
1181 list<ThreadID>::iterator end = activeThreads->end();
1182
1183 while (threads != end) {
1184 ThreadID tid = *threads++;
1185 fetchRedirect[tid] = false;
1186 }
1187
1188 // Uncomment this if you want to see all available instructions.
1189 // @todo This doesn't actually work anymore, we should fix it.
1190// printAvailableInsts();
1191
1192 // Execute/writeback any instructions that are available.
1193 int insts_to_execute = fromIssue->size;
1194 int inst_num = 0;
1195 for (; inst_num < insts_to_execute;
1196 ++inst_num) {
1197
1198 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1199
1200 DynInstPtr inst = instQueue.getInstToExecute();
1201
1202 DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n",
1203 inst->pcState(), inst->threadNumber,inst->seqNum);
1204
1205 // Notify potential listeners that this instruction has started
1206 // executing
1207 ppExecute->notify(inst);
1208
1209 // Check if the instruction is squashed; if so then skip it
1210 if (inst->isSquashed()) {
1211 DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]"
1212 " [sn:%i]\n", inst->pcState(), inst->threadNumber,
1213 inst->seqNum);
1214
1215 // Consider this instruction executed so that commit can go
1216 // ahead and retire the instruction.
1217 inst->setExecuted();
1218
1219 // Not sure if I should set this here or just let commit try to
1220 // commit any squashed instructions. I like the latter a bit more.
1221 inst->setCanCommit();
1222
1223 ++iewExecSquashedInsts;
1224
1225 continue;
1226 }
1227
1228 Fault fault = NoFault;
1229
1230 // Execute instruction.
1231 // Note that if the instruction faults, it will be handled
1232 // at the commit stage.
1233 if (inst->isMemRef()) {
1234 DPRINTF(IEW, "Execute: Calculating address for memory "
1235 "reference.\n");
1236
1237 // Tell the LDSTQ to execute this instruction (if it is a load).
1238 if (inst->isLoad()) {
1239 // Loads will mark themselves as executed, and their writeback
1240 // event adds the instruction to the queue to commit
1241 fault = ldstQueue.executeLoad(inst);
1242
1243 if (inst->isTranslationDelayed() &&
1244 fault == NoFault) {
1245 // A hw page table walk is currently going on; the
1246 // instruction must be deferred.
1247 DPRINTF(IEW, "Execute: Delayed translation, deferring "
1248 "load.\n");
1249 instQueue.deferMemInst(inst);
1250 continue;
1251 }
1252
1253 if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
1254 inst->fault = NoFault;
1255 }
1256 } else if (inst->isStore()) {
1257 fault = ldstQueue.executeStore(inst);
1258
1259 if (inst->isTranslationDelayed() &&
1260 fault == NoFault) {
1261 // A hw page table walk is currently going on; the
1262 // instruction must be deferred.
1263 DPRINTF(IEW, "Execute: Delayed translation, deferring "
1264 "store.\n");
1265 instQueue.deferMemInst(inst);
1266 continue;
1267 }
1268
1269 // If the store had a fault then it may not have a mem req
1270 if (fault != NoFault || !inst->readPredicate() ||
1271 !inst->isStoreConditional()) {
1272 // If the instruction faulted, then we need to send it along
1273 // to commit without the instruction completing.
1274 // Send this instruction to commit, also make sure iew stage
1275 // realizes there is activity.
1276 inst->setExecuted();
1277 instToCommit(inst);
1278 activityThisCycle();
1279 }
1280
1281 // Store conditionals will mark themselves as
1282 // executed, and their writeback event will add the
1283 // instruction to the queue to commit.
1284 } else {
1285 panic("Unexpected memory type!\n");
1286 }
1287
1288 } else {
1289 // If the instruction has already faulted, then skip executing it.
1290 // Such case can happen when it faulted during ITLB translation.
1291 // If we execute the instruction (even if it's a nop) the fault
1292 // will be replaced and we will lose it.
1293 if (inst->getFault() == NoFault) {
1294 inst->execute();
1295 if (!inst->readPredicate())
1296 inst->forwardOldRegs();
1297 }
1298
1299 inst->setExecuted();
1300
1301 instToCommit(inst);
1302 }
1303
1304 updateExeInstStats(inst);
1305
1306 // Check if branch prediction was correct, if not then we need
1307 // to tell commit to squash in flight instructions. Only
1308 // handle this if there hasn't already been something that
1309 // redirects fetch in this group of instructions.
1310
1311 // This probably needs to prioritize the redirects if a different
1312 // scheduler is used. Currently the scheduler schedules the oldest
1313 // instruction first, so the branch resolution order will be correct.
1314 ThreadID tid = inst->threadNumber;
1315
1316 if (!fetchRedirect[tid] ||
1317 !toCommit->squash[tid] ||
1318 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1319
1320 // Prevent testing for misprediction on load instructions,
1321 // that have not been executed.
1322 bool loadNotExecuted = !inst->isExecuted() && inst->isLoad();
1323
1324 if (inst->mispredicted() && !loadNotExecuted) {
1325 fetchRedirect[tid] = true;
1326
1327 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1328 DPRINTF(IEW, "Predicted target was PC: %s.\n",
1329 inst->readPredTarg());
1330 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
1331 inst->pcState());
1332 // If incorrect, then signal the ROB that it must be squashed.
1333 squashDueToBranch(inst, tid);
1334
1335 ppMispredict->notify(inst);
1336
1337 if (inst->readPredTaken()) {
1338 predictedTakenIncorrect++;
1339 } else {
1340 predictedNotTakenIncorrect++;
1341 }
1342 } else if (ldstQueue.violation(tid)) {
1343 assert(inst->isMemRef());
1344 // If there was an ordering violation, then get the
1345 // DynInst that caused the violation. Note that this
1346 // clears the violation signal.
1347 DynInstPtr violator;
1348 violator = ldstQueue.getMemDepViolator(tid);
1349
1350 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s "
1351 "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n",
1352 violator->pcState(), violator->seqNum,
1353 inst->pcState(), inst->seqNum, inst->physEffAddrLow);
1354
1355 fetchRedirect[tid] = true;
1356
1357 // Tell the instruction queue that a violation has occured.
1358 instQueue.violation(inst, violator);
1359
1360 // Squash.
1361 squashDueToMemOrder(violator, tid);
1362
1363 ++memOrderViolationEvents;
1364 }
1365 } else {
1366 // Reset any state associated with redirects that will not
1367 // be used.
1368 if (ldstQueue.violation(tid)) {
1369 assert(inst->isMemRef());
1370
1371 DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1372
1373 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1374 "%s, inst PC: %s. Addr is: %#x.\n",
1375 violator->pcState(), inst->pcState(),
1376 inst->physEffAddrLow);
1377 DPRINTF(IEW, "Violation will not be handled because "
1378 "already squashing\n");
1379
1380 ++memOrderViolationEvents;
1381 }
1382 }
1383 }
1384
1385 // Update and record activity if we processed any instructions.
1386 if (inst_num) {
1387 if (exeStatus == Idle) {
1388 exeStatus = Running;
1389 }
1390
1391 updatedQueues = true;
1392
1393 cpu->activityThisCycle();
1394 }
1395
1396 // Need to reset this in case a writeback event needs to write into the
1397 // iew queue. That way the writeback event will write into the correct
1398 // spot in the queue.
1399 wbNumInst = 0;
1400
1401}
1402
1403template <class Impl>
1404void
1405DefaultIEW<Impl>::writebackInsts()
1406{
1407 // Loop through the head of the time buffer and wake any
1408 // dependents. These instructions are about to write back. Also
1409 // mark scoreboard that this instruction is finally complete.
1410 // Either have IEW have direct access to scoreboard, or have this
1411 // as part of backwards communication.
1412 for (int inst_num = 0; inst_num < wbWidth &&
1413 toCommit->insts[inst_num]; inst_num++) {
1414 DynInstPtr inst = toCommit->insts[inst_num];
1415 ThreadID tid = inst->threadNumber;
1416
1417 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n",
1418 inst->seqNum, inst->pcState());
1419
1420 iewInstsToCommit[tid]++;
1421 // Notify potential listeners that execution is complete for this
1422 // instruction.
1423 ppToCommit->notify(inst);
1424
1425 // Some instructions will be sent to commit without having
1426 // executed because they need commit to handle them.
1427 // E.g. Strictly ordered loads have not actually executed when they
1428 // are first sent to commit. Instead commit must tell the LSQ
1429 // when it's ready to execute the strictly ordered load.
1430 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1431 int dependents = instQueue.wakeDependents(inst);
1432
1433 for (int i = 0; i < inst->numDestRegs(); i++) {
1434 //mark as Ready
1435 DPRINTF(IEW,"Setting Destination Register %i\n",
1436 inst->renamedDestRegIdx(i));
1437 scoreboard->setReg(inst->renamedDestRegIdx(i));
1438 }
1439
1440 if (dependents) {
1441 producerInst[tid]++;
1442 consumerInst[tid]+= dependents;
1443 }
1444 writebackCount[tid]++;
1445 }
1446 }
1447}
1448
1449template<class Impl>
1450void
1451DefaultIEW<Impl>::tick()
1452{
1453 wbNumInst = 0;
1454 wbCycle = 0;
1455
1456 wroteToTimeBuffer = false;
1457 updatedQueues = false;
1458
1459 sortInsts();
1460
1461 // Free function units marked as being freed this cycle.
1462 fuPool->processFreeUnits();
1463
1464 list<ThreadID>::iterator threads = activeThreads->begin();
1465 list<ThreadID>::iterator end = activeThreads->end();
1466
1467 // Check stall and squash signals, dispatch any instructions.
1468 while (threads != end) {
1469 ThreadID tid = *threads++;
1470
1471 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1472
1473 checkSignalsAndUpdate(tid);
1474 dispatch(tid);
1475 }
1476
1477 if (exeStatus != Squashing) {
1478 executeInsts();
1479
1480 writebackInsts();
1481
1482 // Have the instruction queue try to schedule any ready instructions.
1483 // (In actuality, this scheduling is for instructions that will
1484 // be executed next cycle.)
1485 instQueue.scheduleReadyInsts();
1486
1487 // Also should advance its own time buffers if the stage ran.
1488 // Not the best place for it, but this works (hopefully).
1489 issueToExecQueue.advance();
1490 }
1491
1492 bool broadcast_free_entries = false;
1493
1494 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1495 exeStatus = Idle;
1496 updateLSQNextCycle = false;
1497
1498 broadcast_free_entries = true;
1499 }
1500
1501 // Writeback any stores using any leftover bandwidth.
1502 ldstQueue.writebackStores();
1503
1504 // Check the committed load/store signals to see if there's a load
1505 // or store to commit. Also check if it's being told to execute a
1506 // nonspeculative instruction.
1507 // This is pretty inefficient...
1508
1509 threads = activeThreads->begin();
1510 while (threads != end) {
1511 ThreadID tid = (*threads++);
1512
1513 DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1514
1515 // Update structures based on instructions committed.
1516 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1517 !fromCommit->commitInfo[tid].squash &&
1518 !fromCommit->commitInfo[tid].robSquashing) {
1519
1520 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1521
1522 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1523
1524 updateLSQNextCycle = true;
1525 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1526 }
1527
1528 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1529
1530 //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1531 if (fromCommit->commitInfo[tid].strictlyOrdered) {
1532 instQueue.replayMemInst(
1533 fromCommit->commitInfo[tid].strictlyOrderedLoad);
1534 fromCommit->commitInfo[tid].strictlyOrderedLoad->setAtCommit();
1535 } else {
1536 instQueue.scheduleNonSpec(
1537 fromCommit->commitInfo[tid].nonSpecSeqNum);
1538 }
1539 }
1540
1541 if (broadcast_free_entries) {
1542 toFetch->iewInfo[tid].iqCount =
1543 instQueue.getCount(tid);
1544 toFetch->iewInfo[tid].ldstqCount =
1545 ldstQueue.getCount(tid);
1546
1547 toRename->iewInfo[tid].usedIQ = true;
1548 toRename->iewInfo[tid].freeIQEntries =
1549 instQueue.numFreeEntries(tid);
1550 toRename->iewInfo[tid].usedLSQ = true;
1551
1552 toRename->iewInfo[tid].freeLQEntries =
1553 ldstQueue.numFreeLoadEntries(tid);
1554 toRename->iewInfo[tid].freeSQEntries =
1555 ldstQueue.numFreeStoreEntries(tid);
1556
1557 wroteToTimeBuffer = true;
1558 }
1559
1560 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1561 tid, toRename->iewInfo[tid].dispatched);
1562 }
1563
1564 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). "
1565 "LQ has %i free entries. SQ has %i free entries.\n",
1566 instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1567 ldstQueue.numFreeLoadEntries(), ldstQueue.numFreeStoreEntries());
1568
1569 updateStatus();
1570
1571 if (wroteToTimeBuffer) {
1572 DPRINTF(Activity, "Activity this cycle.\n");
1573 cpu->activityThisCycle();
1574 }
1575}
1576
1577template <class Impl>
1578void
1579DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1580{
1581 ThreadID tid = inst->threadNumber;
1582
1583 iewExecutedInsts++;
1584
1585#if TRACING_ON
1586 if (DTRACE(O3PipeView)) {
1587 inst->completeTick = curTick() - inst->fetchTick;
1588 }
1589#endif
1590
1591 //
1592 // Control operations
1593 //
1594 if (inst->isControl())
1595 iewExecutedBranches[tid]++;
1596
1597 //
1598 // Memory operations
1599 //
1600 if (inst->isMemRef()) {
1601 iewExecutedRefs[tid]++;
1602
1603 if (inst->isLoad()) {
1604 iewExecLoadInsts[tid]++;
1605 }
1606 }
1607}
1608
1609template <class Impl>
1610void
1611DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
1612{
1613 ThreadID tid = inst->threadNumber;
1614
1615 if (!fetchRedirect[tid] ||
1616 !toCommit->squash[tid] ||
1617 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1618
1619 if (inst->mispredicted()) {
1620 fetchRedirect[tid] = true;
1621
1622 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1623 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1624 inst->predInstAddr(), inst->predNextInstAddr());
1625 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
1626 " NPC: %#x.\n", inst->nextInstAddr(),
1627 inst->nextInstAddr());
1628 // If incorrect, then signal the ROB that it must be squashed.
1629 squashDueToBranch(inst, tid);
1630
1631 if (inst->readPredTaken()) {
1632 predictedTakenIncorrect++;
1633 } else {
1634 predictedNotTakenIncorrect++;
1635 }
1636 }
1637 }
1638}
1639
1640#endif//__CPU_O3_IEW_IMPL_IMPL_HH__
2 * Copyright (c) 2010-2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_O3_IEW_IMPL_IMPL_HH__
45#define __CPU_O3_IEW_IMPL_IMPL_HH__
46
47// @todo: Fix the instantaneous communication among all the stages within
48// iew. There's a clear delay between issue and execute, yet backwards
49// communication happens simultaneously.
50
51#include <queue>
52
53#include "arch/utility.hh"
54#include "config/the_isa.hh"
55#include "cpu/checker/cpu.hh"
56#include "cpu/o3/fu_pool.hh"
57#include "cpu/o3/iew.hh"
58#include "cpu/timebuf.hh"
59#include "debug/Activity.hh"
60#include "debug/Drain.hh"
61#include "debug/IEW.hh"
62#include "debug/O3PipeView.hh"
63#include "params/DerivO3CPU.hh"
64
65using namespace std;
66
67template<class Impl>
68DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
69 : issueToExecQueue(params->backComSize, params->forwardComSize),
70 cpu(_cpu),
71 instQueue(_cpu, this, params),
72 ldstQueue(_cpu, this, params),
73 fuPool(params->fuPool),
74 commitToIEWDelay(params->commitToIEWDelay),
75 renameToIEWDelay(params->renameToIEWDelay),
76 issueToExecuteDelay(params->issueToExecuteDelay),
77 dispatchWidth(params->dispatchWidth),
78 issueWidth(params->issueWidth),
79 wbWidth(params->wbWidth),
80 numThreads(params->numThreads)
81{
82 if (dispatchWidth > Impl::MaxWidth)
83 fatal("dispatchWidth (%d) is larger than compiled limit (%d),\n"
84 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
85 dispatchWidth, static_cast<int>(Impl::MaxWidth));
86 if (issueWidth > Impl::MaxWidth)
87 fatal("issueWidth (%d) is larger than compiled limit (%d),\n"
88 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
89 issueWidth, static_cast<int>(Impl::MaxWidth));
90 if (wbWidth > Impl::MaxWidth)
91 fatal("wbWidth (%d) is larger than compiled limit (%d),\n"
92 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
93 wbWidth, static_cast<int>(Impl::MaxWidth));
94
95 _status = Active;
96 exeStatus = Running;
97 wbStatus = Idle;
98
99 // Setup wire to read instructions coming from issue.
100 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
101
102 // Instruction queue needs the queue between issue and execute.
103 instQueue.setIssueToExecuteQueue(&issueToExecQueue);
104
105 for (ThreadID tid = 0; tid < numThreads; tid++) {
106 dispatchStatus[tid] = Running;
107 fetchRedirect[tid] = false;
108 }
109
110 updateLSQNextCycle = false;
111
112 skidBufferMax = (renameToIEWDelay + 1) * params->renameWidth;
113}
114
115template <class Impl>
116std::string
117DefaultIEW<Impl>::name() const
118{
119 return cpu->name() + ".iew";
120}
121
122template <class Impl>
123void
124DefaultIEW<Impl>::regProbePoints()
125{
126 ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch");
127 ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict");
128 /**
129 * Probe point with dynamic instruction as the argument used to probe when
130 * an instruction starts to execute.
131 */
132 ppExecute = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(),
133 "Execute");
134 /**
135 * Probe point with dynamic instruction as the argument used to probe when
136 * an instruction execution completes and it is marked ready to commit.
137 */
138 ppToCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(),
139 "ToCommit");
140}
141
142template <class Impl>
143void
144DefaultIEW<Impl>::regStats()
145{
146 using namespace Stats;
147
148 instQueue.regStats();
149 ldstQueue.regStats();
150
151 iewIdleCycles
152 .name(name() + ".iewIdleCycles")
153 .desc("Number of cycles IEW is idle");
154
155 iewSquashCycles
156 .name(name() + ".iewSquashCycles")
157 .desc("Number of cycles IEW is squashing");
158
159 iewBlockCycles
160 .name(name() + ".iewBlockCycles")
161 .desc("Number of cycles IEW is blocking");
162
163 iewUnblockCycles
164 .name(name() + ".iewUnblockCycles")
165 .desc("Number of cycles IEW is unblocking");
166
167 iewDispatchedInsts
168 .name(name() + ".iewDispatchedInsts")
169 .desc("Number of instructions dispatched to IQ");
170
171 iewDispSquashedInsts
172 .name(name() + ".iewDispSquashedInsts")
173 .desc("Number of squashed instructions skipped by dispatch");
174
175 iewDispLoadInsts
176 .name(name() + ".iewDispLoadInsts")
177 .desc("Number of dispatched load instructions");
178
179 iewDispStoreInsts
180 .name(name() + ".iewDispStoreInsts")
181 .desc("Number of dispatched store instructions");
182
183 iewDispNonSpecInsts
184 .name(name() + ".iewDispNonSpecInsts")
185 .desc("Number of dispatched non-speculative instructions");
186
187 iewIQFullEvents
188 .name(name() + ".iewIQFullEvents")
189 .desc("Number of times the IQ has become full, causing a stall");
190
191 iewLSQFullEvents
192 .name(name() + ".iewLSQFullEvents")
193 .desc("Number of times the LSQ has become full, causing a stall");
194
195 memOrderViolationEvents
196 .name(name() + ".memOrderViolationEvents")
197 .desc("Number of memory order violations");
198
199 predictedTakenIncorrect
200 .name(name() + ".predictedTakenIncorrect")
201 .desc("Number of branches that were predicted taken incorrectly");
202
203 predictedNotTakenIncorrect
204 .name(name() + ".predictedNotTakenIncorrect")
205 .desc("Number of branches that were predicted not taken incorrectly");
206
207 branchMispredicts
208 .name(name() + ".branchMispredicts")
209 .desc("Number of branch mispredicts detected at execute");
210
211 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
212
213 iewExecutedInsts
214 .name(name() + ".iewExecutedInsts")
215 .desc("Number of executed instructions");
216
217 iewExecLoadInsts
218 .init(cpu->numThreads)
219 .name(name() + ".iewExecLoadInsts")
220 .desc("Number of load instructions executed")
221 .flags(total);
222
223 iewExecSquashedInsts
224 .name(name() + ".iewExecSquashedInsts")
225 .desc("Number of squashed instructions skipped in execute");
226
227 iewExecutedSwp
228 .init(cpu->numThreads)
229 .name(name() + ".exec_swp")
230 .desc("number of swp insts executed")
231 .flags(total);
232
233 iewExecutedNop
234 .init(cpu->numThreads)
235 .name(name() + ".exec_nop")
236 .desc("number of nop insts executed")
237 .flags(total);
238
239 iewExecutedRefs
240 .init(cpu->numThreads)
241 .name(name() + ".exec_refs")
242 .desc("number of memory reference insts executed")
243 .flags(total);
244
245 iewExecutedBranches
246 .init(cpu->numThreads)
247 .name(name() + ".exec_branches")
248 .desc("Number of branches executed")
249 .flags(total);
250
251 iewExecStoreInsts
252 .name(name() + ".exec_stores")
253 .desc("Number of stores executed")
254 .flags(total);
255 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
256
257 iewExecRate
258 .name(name() + ".exec_rate")
259 .desc("Inst execution rate")
260 .flags(total);
261
262 iewExecRate = iewExecutedInsts / cpu->numCycles;
263
264 iewInstsToCommit
265 .init(cpu->numThreads)
266 .name(name() + ".wb_sent")
267 .desc("cumulative count of insts sent to commit")
268 .flags(total);
269
270 writebackCount
271 .init(cpu->numThreads)
272 .name(name() + ".wb_count")
273 .desc("cumulative count of insts written-back")
274 .flags(total);
275
276 producerInst
277 .init(cpu->numThreads)
278 .name(name() + ".wb_producers")
279 .desc("num instructions producing a value")
280 .flags(total);
281
282 consumerInst
283 .init(cpu->numThreads)
284 .name(name() + ".wb_consumers")
285 .desc("num instructions consuming a value")
286 .flags(total);
287
288 wbFanout
289 .name(name() + ".wb_fanout")
290 .desc("average fanout of values written-back")
291 .flags(total);
292
293 wbFanout = producerInst / consumerInst;
294
295 wbRate
296 .name(name() + ".wb_rate")
297 .desc("insts written-back per cycle")
298 .flags(total);
299 wbRate = writebackCount / cpu->numCycles;
300}
301
302template<class Impl>
303void
304DefaultIEW<Impl>::startupStage()
305{
306 for (ThreadID tid = 0; tid < numThreads; tid++) {
307 toRename->iewInfo[tid].usedIQ = true;
308 toRename->iewInfo[tid].freeIQEntries =
309 instQueue.numFreeEntries(tid);
310
311 toRename->iewInfo[tid].usedLSQ = true;
312 toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid);
313 toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid);
314 }
315
316 // Initialize the checker's dcache port here
317 if (cpu->checker) {
318 cpu->checker->setDcachePort(&cpu->getDataPort());
319 }
320
321 cpu->activateStage(O3CPU::IEWIdx);
322}
323
324template<class Impl>
325void
326DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
327{
328 timeBuffer = tb_ptr;
329
330 // Setup wire to read information from time buffer, from commit.
331 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
332
333 // Setup wire to write information back to previous stages.
334 toRename = timeBuffer->getWire(0);
335
336 toFetch = timeBuffer->getWire(0);
337
338 // Instruction queue also needs main time buffer.
339 instQueue.setTimeBuffer(tb_ptr);
340}
341
342template<class Impl>
343void
344DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
345{
346 renameQueue = rq_ptr;
347
348 // Setup wire to read information from rename queue.
349 fromRename = renameQueue->getWire(-renameToIEWDelay);
350}
351
352template<class Impl>
353void
354DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
355{
356 iewQueue = iq_ptr;
357
358 // Setup wire to write instructions to commit.
359 toCommit = iewQueue->getWire(0);
360}
361
362template<class Impl>
363void
364DefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
365{
366 activeThreads = at_ptr;
367
368 ldstQueue.setActiveThreads(at_ptr);
369 instQueue.setActiveThreads(at_ptr);
370}
371
372template<class Impl>
373void
374DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
375{
376 scoreboard = sb_ptr;
377}
378
379template <class Impl>
380bool
381DefaultIEW<Impl>::isDrained() const
382{
383 bool drained = ldstQueue.isDrained() && instQueue.isDrained();
384
385 for (ThreadID tid = 0; tid < numThreads; tid++) {
386 if (!insts[tid].empty()) {
387 DPRINTF(Drain, "%i: Insts not empty.\n", tid);
388 drained = false;
389 }
390 if (!skidBuffer[tid].empty()) {
391 DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid);
392 drained = false;
393 }
394 }
395
396 // Also check the FU pool as instructions are "stored" in FU
397 // completion events until they are done and not accounted for
398 // above
399 if (drained && !fuPool->isDrained()) {
400 DPRINTF(Drain, "FU pool still busy.\n");
401 drained = false;
402 }
403
404 return drained;
405}
406
407template <class Impl>
408void
409DefaultIEW<Impl>::drainSanityCheck() const
410{
411 assert(isDrained());
412
413 instQueue.drainSanityCheck();
414 ldstQueue.drainSanityCheck();
415}
416
417template <class Impl>
418void
419DefaultIEW<Impl>::takeOverFrom()
420{
421 // Reset all state.
422 _status = Active;
423 exeStatus = Running;
424 wbStatus = Idle;
425
426 instQueue.takeOverFrom();
427 ldstQueue.takeOverFrom();
428 fuPool->takeOverFrom();
429
430 startupStage();
431 cpu->activityThisCycle();
432
433 for (ThreadID tid = 0; tid < numThreads; tid++) {
434 dispatchStatus[tid] = Running;
435 fetchRedirect[tid] = false;
436 }
437
438 updateLSQNextCycle = false;
439
440 for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
441 issueToExecQueue.advance();
442 }
443}
444
445template<class Impl>
446void
447DefaultIEW<Impl>::squash(ThreadID tid)
448{
449 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid);
450
451 // Tell the IQ to start squashing.
452 instQueue.squash(tid);
453
454 // Tell the LDSTQ to start squashing.
455 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
456 updatedQueues = true;
457
458 // Clear the skid buffer in case it has any data in it.
459 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
460 tid, fromCommit->commitInfo[tid].doneSeqNum);
461
462 while (!skidBuffer[tid].empty()) {
463 if (skidBuffer[tid].front()->isLoad()) {
464 toRename->iewInfo[tid].dispatchedToLQ++;
465 }
466 if (skidBuffer[tid].front()->isStore()) {
467 toRename->iewInfo[tid].dispatchedToSQ++;
468 }
469
470 toRename->iewInfo[tid].dispatched++;
471
472 skidBuffer[tid].pop();
473 }
474
475 emptyRenameInsts(tid);
476}
477
478template<class Impl>
479void
480DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
481{
482 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
483 "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
484
485 if (!toCommit->squash[tid] ||
486 inst->seqNum < toCommit->squashedSeqNum[tid]) {
487 toCommit->squash[tid] = true;
488 toCommit->squashedSeqNum[tid] = inst->seqNum;
489 toCommit->branchTaken[tid] = inst->pcState().branching();
490
491 TheISA::PCState pc = inst->pcState();
492 TheISA::advancePC(pc, inst->staticInst);
493
494 toCommit->pc[tid] = pc;
495 toCommit->mispredictInst[tid] = inst;
496 toCommit->includeSquashInst[tid] = false;
497
498 wroteToTimeBuffer = true;
499 }
500
501}
502
503template<class Impl>
504void
505DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
506{
507 DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger "
508 "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
509 // Need to include inst->seqNum in the following comparison to cover the
510 // corner case when a branch misprediction and a memory violation for the
511 // same instruction (e.g. load PC) are detected in the same cycle. In this
512 // case the memory violator should take precedence over the branch
513 // misprediction because it requires the violator itself to be included in
514 // the squash.
515 if (!toCommit->squash[tid] ||
516 inst->seqNum <= toCommit->squashedSeqNum[tid]) {
517 toCommit->squash[tid] = true;
518
519 toCommit->squashedSeqNum[tid] = inst->seqNum;
520 toCommit->pc[tid] = inst->pcState();
521 toCommit->mispredictInst[tid] = NULL;
522
523 // Must include the memory violator in the squash.
524 toCommit->includeSquashInst[tid] = true;
525
526 wroteToTimeBuffer = true;
527 }
528}
529
530template<class Impl>
531void
532DefaultIEW<Impl>::block(ThreadID tid)
533{
534 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
535
536 if (dispatchStatus[tid] != Blocked &&
537 dispatchStatus[tid] != Unblocking) {
538 toRename->iewBlock[tid] = true;
539 wroteToTimeBuffer = true;
540 }
541
542 // Add the current inputs to the skid buffer so they can be
543 // reprocessed when this stage unblocks.
544 skidInsert(tid);
545
546 dispatchStatus[tid] = Blocked;
547}
548
549template<class Impl>
550void
551DefaultIEW<Impl>::unblock(ThreadID tid)
552{
553 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
554 "buffer %u.\n",tid, tid);
555
556 // If the skid bufffer is empty, signal back to previous stages to unblock.
557 // Also switch status to running.
558 if (skidBuffer[tid].empty()) {
559 toRename->iewUnblock[tid] = true;
560 wroteToTimeBuffer = true;
561 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
562 dispatchStatus[tid] = Running;
563 }
564}
565
566template<class Impl>
567void
568DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
569{
570 instQueue.wakeDependents(inst);
571}
572
573template<class Impl>
574void
575DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
576{
577 instQueue.rescheduleMemInst(inst);
578}
579
580template<class Impl>
581void
582DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
583{
584 instQueue.replayMemInst(inst);
585}
586
587template<class Impl>
588void
589DefaultIEW<Impl>::blockMemInst(DynInstPtr& inst)
590{
591 instQueue.blockMemInst(inst);
592}
593
594template<class Impl>
595void
596DefaultIEW<Impl>::cacheUnblocked()
597{
598 instQueue.cacheUnblocked();
599}
600
601template<class Impl>
602void
603DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
604{
605 // This function should not be called after writebackInsts in a
606 // single cycle. That will cause problems with an instruction
607 // being added to the queue to commit without being processed by
608 // writebackInsts prior to being sent to commit.
609
610 // First check the time slot that this instruction will write
611 // to. If there are free write ports at the time, then go ahead
612 // and write the instruction to that time. If there are not,
613 // keep looking back to see where's the first time there's a
614 // free slot.
615 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
616 ++wbNumInst;
617 if (wbNumInst == wbWidth) {
618 ++wbCycle;
619 wbNumInst = 0;
620 }
621 }
622
623 DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
624 wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
625 // Add finished instruction to queue to commit.
626 (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
627 (*iewQueue)[wbCycle].size++;
628}
629
630template <class Impl>
631unsigned
632DefaultIEW<Impl>::validInstsFromRename()
633{
634 unsigned inst_count = 0;
635
636 for (int i=0; i<fromRename->size; i++) {
637 if (!fromRename->insts[i]->isSquashed())
638 inst_count++;
639 }
640
641 return inst_count;
642}
643
644template<class Impl>
645void
646DefaultIEW<Impl>::skidInsert(ThreadID tid)
647{
648 DynInstPtr inst = NULL;
649
650 while (!insts[tid].empty()) {
651 inst = insts[tid].front();
652
653 insts[tid].pop();
654
655 DPRINTF(IEW,"[tid:%i]: Inserting [sn:%lli] PC:%s into "
656 "dispatch skidBuffer %i\n",tid, inst->seqNum,
657 inst->pcState(),tid);
658
659 skidBuffer[tid].push(inst);
660 }
661
662 assert(skidBuffer[tid].size() <= skidBufferMax &&
663 "Skidbuffer Exceeded Max Size");
664}
665
666template<class Impl>
667int
668DefaultIEW<Impl>::skidCount()
669{
670 int max=0;
671
672 list<ThreadID>::iterator threads = activeThreads->begin();
673 list<ThreadID>::iterator end = activeThreads->end();
674
675 while (threads != end) {
676 ThreadID tid = *threads++;
677 unsigned thread_count = skidBuffer[tid].size();
678 if (max < thread_count)
679 max = thread_count;
680 }
681
682 return max;
683}
684
685template<class Impl>
686bool
687DefaultIEW<Impl>::skidsEmpty()
688{
689 list<ThreadID>::iterator threads = activeThreads->begin();
690 list<ThreadID>::iterator end = activeThreads->end();
691
692 while (threads != end) {
693 ThreadID tid = *threads++;
694
695 if (!skidBuffer[tid].empty())
696 return false;
697 }
698
699 return true;
700}
701
702template <class Impl>
703void
704DefaultIEW<Impl>::updateStatus()
705{
706 bool any_unblocking = false;
707
708 list<ThreadID>::iterator threads = activeThreads->begin();
709 list<ThreadID>::iterator end = activeThreads->end();
710
711 while (threads != end) {
712 ThreadID tid = *threads++;
713
714 if (dispatchStatus[tid] == Unblocking) {
715 any_unblocking = true;
716 break;
717 }
718 }
719
720 // If there are no ready instructions waiting to be scheduled by the IQ,
721 // and there's no stores waiting to write back, and dispatch is not
722 // unblocking, then there is no internal activity for the IEW stage.
723 instQueue.intInstQueueReads++;
724 if (_status == Active && !instQueue.hasReadyInsts() &&
725 !ldstQueue.willWB() && !any_unblocking) {
726 DPRINTF(IEW, "IEW switching to idle\n");
727
728 deactivateStage();
729
730 _status = Inactive;
731 } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
732 ldstQueue.willWB() ||
733 any_unblocking)) {
734 // Otherwise there is internal activity. Set to active.
735 DPRINTF(IEW, "IEW switching to active\n");
736
737 activateStage();
738
739 _status = Active;
740 }
741}
742
743template <class Impl>
744void
745DefaultIEW<Impl>::resetEntries()
746{
747 instQueue.resetEntries();
748 ldstQueue.resetEntries();
749}
750
751template <class Impl>
752bool
753DefaultIEW<Impl>::checkStall(ThreadID tid)
754{
755 bool ret_val(false);
756
757 if (fromCommit->commitInfo[tid].robSquashing) {
758 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
759 ret_val = true;
760 } else if (instQueue.isFull(tid)) {
761 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid);
762 ret_val = true;
763 }
764
765 return ret_val;
766}
767
768template <class Impl>
769void
770DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
771{
772 // Check if there's a squash signal, squash if there is
773 // Check stall signals, block if there is.
774 // If status was Blocked
775 // if so then go to unblocking
776 // If status was Squashing
777 // check if squashing is not high. Switch to running this cycle.
778
779 if (fromCommit->commitInfo[tid].squash) {
780 squash(tid);
781
782 if (dispatchStatus[tid] == Blocked ||
783 dispatchStatus[tid] == Unblocking) {
784 toRename->iewUnblock[tid] = true;
785 wroteToTimeBuffer = true;
786 }
787
788 dispatchStatus[tid] = Squashing;
789 fetchRedirect[tid] = false;
790 return;
791 }
792
793 if (fromCommit->commitInfo[tid].robSquashing) {
794 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
795
796 dispatchStatus[tid] = Squashing;
797 emptyRenameInsts(tid);
798 wroteToTimeBuffer = true;
799 }
800
801 if (checkStall(tid)) {
802 block(tid);
803 dispatchStatus[tid] = Blocked;
804 return;
805 }
806
807 if (dispatchStatus[tid] == Blocked) {
808 // Status from previous cycle was blocked, but there are no more stall
809 // conditions. Switch over to unblocking.
810 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
811 tid);
812
813 dispatchStatus[tid] = Unblocking;
814
815 unblock(tid);
816
817 return;
818 }
819
820 if (dispatchStatus[tid] == Squashing) {
821 // Switch status to running if rename isn't being told to block or
822 // squash this cycle.
823 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
824 tid);
825
826 dispatchStatus[tid] = Running;
827
828 return;
829 }
830}
831
832template <class Impl>
833void
834DefaultIEW<Impl>::sortInsts()
835{
836 int insts_from_rename = fromRename->size;
837#ifdef DEBUG
838 for (ThreadID tid = 0; tid < numThreads; tid++)
839 assert(insts[tid].empty());
840#endif
841 for (int i = 0; i < insts_from_rename; ++i) {
842 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
843 }
844}
845
846template <class Impl>
847void
848DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid)
849{
850 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
851
852 while (!insts[tid].empty()) {
853
854 if (insts[tid].front()->isLoad()) {
855 toRename->iewInfo[tid].dispatchedToLQ++;
856 }
857 if (insts[tid].front()->isStore()) {
858 toRename->iewInfo[tid].dispatchedToSQ++;
859 }
860
861 toRename->iewInfo[tid].dispatched++;
862
863 insts[tid].pop();
864 }
865}
866
867template <class Impl>
868void
869DefaultIEW<Impl>::wakeCPU()
870{
871 cpu->wakeCPU();
872}
873
874template <class Impl>
875void
876DefaultIEW<Impl>::activityThisCycle()
877{
878 DPRINTF(Activity, "Activity this cycle.\n");
879 cpu->activityThisCycle();
880}
881
882template <class Impl>
883inline void
884DefaultIEW<Impl>::activateStage()
885{
886 DPRINTF(Activity, "Activating stage.\n");
887 cpu->activateStage(O3CPU::IEWIdx);
888}
889
890template <class Impl>
891inline void
892DefaultIEW<Impl>::deactivateStage()
893{
894 DPRINTF(Activity, "Deactivating stage.\n");
895 cpu->deactivateStage(O3CPU::IEWIdx);
896}
897
898template<class Impl>
899void
900DefaultIEW<Impl>::dispatch(ThreadID tid)
901{
902 // If status is Running or idle,
903 // call dispatchInsts()
904 // If status is Unblocking,
905 // buffer any instructions coming from rename
906 // continue trying to empty skid buffer
907 // check if stall conditions have passed
908
909 if (dispatchStatus[tid] == Blocked) {
910 ++iewBlockCycles;
911
912 } else if (dispatchStatus[tid] == Squashing) {
913 ++iewSquashCycles;
914 }
915
916 // Dispatch should try to dispatch as many instructions as its bandwidth
917 // will allow, as long as it is not currently blocked.
918 if (dispatchStatus[tid] == Running ||
919 dispatchStatus[tid] == Idle) {
920 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
921 "dispatch.\n", tid);
922
923 dispatchInsts(tid);
924 } else if (dispatchStatus[tid] == Unblocking) {
925 // Make sure that the skid buffer has something in it if the
926 // status is unblocking.
927 assert(!skidsEmpty());
928
929 // If the status was unblocking, then instructions from the skid
930 // buffer were used. Remove those instructions and handle
931 // the rest of unblocking.
932 dispatchInsts(tid);
933
934 ++iewUnblockCycles;
935
936 if (validInstsFromRename()) {
937 // Add the current inputs to the skid buffer so they can be
938 // reprocessed when this stage unblocks.
939 skidInsert(tid);
940 }
941
942 unblock(tid);
943 }
944}
945
946template <class Impl>
947void
948DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
949{
950 // Obtain instructions from skid buffer if unblocking, or queue from rename
951 // otherwise.
952 std::queue<DynInstPtr> &insts_to_dispatch =
953 dispatchStatus[tid] == Unblocking ?
954 skidBuffer[tid] : insts[tid];
955
956 int insts_to_add = insts_to_dispatch.size();
957
958 DynInstPtr inst;
959 bool add_to_iq = false;
960 int dis_num_inst = 0;
961
962 // Loop through the instructions, putting them in the instruction
963 // queue.
964 for ( ; dis_num_inst < insts_to_add &&
965 dis_num_inst < dispatchWidth;
966 ++dis_num_inst)
967 {
968 inst = insts_to_dispatch.front();
969
970 if (dispatchStatus[tid] == Unblocking) {
971 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
972 "buffer\n", tid);
973 }
974
975 // Make sure there's a valid instruction there.
976 assert(inst);
977
978 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to "
979 "IQ.\n",
980 tid, inst->pcState(), inst->seqNum, inst->threadNumber);
981
982 // Be sure to mark these instructions as ready so that the
983 // commit stage can go ahead and execute them, and mark
984 // them as issued so the IQ doesn't reprocess them.
985
986 // Check for squashed instructions.
987 if (inst->isSquashed()) {
988 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
989 "not adding to IQ.\n", tid);
990
991 ++iewDispSquashedInsts;
992
993 insts_to_dispatch.pop();
994
995 //Tell Rename That An Instruction has been processed
996 if (inst->isLoad()) {
997 toRename->iewInfo[tid].dispatchedToLQ++;
998 }
999 if (inst->isStore()) {
1000 toRename->iewInfo[tid].dispatchedToSQ++;
1001 }
1002
1003 toRename->iewInfo[tid].dispatched++;
1004
1005 continue;
1006 }
1007
1008 // Check for full conditions.
1009 if (instQueue.isFull(tid)) {
1010 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1011
1012 // Call function to start blocking.
1013 block(tid);
1014
1015 // Set unblock to false. Special case where we are using
1016 // skidbuffer (unblocking) instructions but then we still
1017 // get full in the IQ.
1018 toRename->iewUnblock[tid] = false;
1019
1020 ++iewIQFullEvents;
1021 break;
1022 }
1023
1024 // Check LSQ if inst is LD/ST
1025 if ((inst->isLoad() && ldstQueue.lqFull(tid)) ||
1026 (inst->isStore() && ldstQueue.sqFull(tid))) {
1027 DPRINTF(IEW, "[tid:%i]: Issue: %s has become full.\n",tid,
1028 inst->isLoad() ? "LQ" : "SQ");
1029
1030 // Call function to start blocking.
1031 block(tid);
1032
1033 // Set unblock to false. Special case where we are using
1034 // skidbuffer (unblocking) instructions but then we still
1035 // get full in the IQ.
1036 toRename->iewUnblock[tid] = false;
1037
1038 ++iewLSQFullEvents;
1039 break;
1040 }
1041
1042 // Otherwise issue the instruction just fine.
1043 if (inst->isLoad()) {
1044 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1045 "encountered, adding to LSQ.\n", tid);
1046
1047 // Reserve a spot in the load store queue for this
1048 // memory access.
1049 ldstQueue.insertLoad(inst);
1050
1051 ++iewDispLoadInsts;
1052
1053 add_to_iq = true;
1054
1055 toRename->iewInfo[tid].dispatchedToLQ++;
1056 } else if (inst->isStore()) {
1057 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1058 "encountered, adding to LSQ.\n", tid);
1059
1060 ldstQueue.insertStore(inst);
1061
1062 ++iewDispStoreInsts;
1063
1064 if (inst->isStoreConditional()) {
1065 // Store conditionals need to be set as "canCommit()"
1066 // so that commit can process them when they reach the
1067 // head of commit.
1068 // @todo: This is somewhat specific to Alpha.
1069 inst->setCanCommit();
1070 instQueue.insertNonSpec(inst);
1071 add_to_iq = false;
1072
1073 ++iewDispNonSpecInsts;
1074 } else {
1075 add_to_iq = true;
1076 }
1077
1078 toRename->iewInfo[tid].dispatchedToSQ++;
1079 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1080 // Same as non-speculative stores.
1081 inst->setCanCommit();
1082 instQueue.insertBarrier(inst);
1083 add_to_iq = false;
1084 } else if (inst->isNop()) {
1085 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1086 "skipping.\n", tid);
1087
1088 inst->setIssued();
1089 inst->setExecuted();
1090 inst->setCanCommit();
1091
1092 instQueue.recordProducer(inst);
1093
1094 iewExecutedNop[tid]++;
1095
1096 add_to_iq = false;
1097 } else {
1098 assert(!inst->isExecuted());
1099 add_to_iq = true;
1100 }
1101
1102 if (inst->isNonSpeculative()) {
1103 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1104 "encountered, skipping.\n", tid);
1105
1106 // Same as non-speculative stores.
1107 inst->setCanCommit();
1108
1109 // Specifically insert it as nonspeculative.
1110 instQueue.insertNonSpec(inst);
1111
1112 ++iewDispNonSpecInsts;
1113
1114 add_to_iq = false;
1115 }
1116
1117 // If the instruction queue is not full, then add the
1118 // instruction.
1119 if (add_to_iq) {
1120 instQueue.insert(inst);
1121 }
1122
1123 insts_to_dispatch.pop();
1124
1125 toRename->iewInfo[tid].dispatched++;
1126
1127 ++iewDispatchedInsts;
1128
1129#if TRACING_ON
1130 inst->dispatchTick = curTick() - inst->fetchTick;
1131#endif
1132 ppDispatch->notify(inst);
1133 }
1134
1135 if (!insts_to_dispatch.empty()) {
1136 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1137 block(tid);
1138 toRename->iewUnblock[tid] = false;
1139 }
1140
1141 if (dispatchStatus[tid] == Idle && dis_num_inst) {
1142 dispatchStatus[tid] = Running;
1143
1144 updatedQueues = true;
1145 }
1146
1147 dis_num_inst = 0;
1148}
1149
1150template <class Impl>
1151void
1152DefaultIEW<Impl>::printAvailableInsts()
1153{
1154 int inst = 0;
1155
1156 std::cout << "Available Instructions: ";
1157
1158 while (fromIssue->insts[inst]) {
1159
1160 if (inst%3==0) std::cout << "\n\t";
1161
1162 std::cout << "PC: " << fromIssue->insts[inst]->pcState()
1163 << " TN: " << fromIssue->insts[inst]->threadNumber
1164 << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1165
1166 inst++;
1167
1168 }
1169
1170 std::cout << "\n";
1171}
1172
1173template <class Impl>
1174void
1175DefaultIEW<Impl>::executeInsts()
1176{
1177 wbNumInst = 0;
1178 wbCycle = 0;
1179
1180 list<ThreadID>::iterator threads = activeThreads->begin();
1181 list<ThreadID>::iterator end = activeThreads->end();
1182
1183 while (threads != end) {
1184 ThreadID tid = *threads++;
1185 fetchRedirect[tid] = false;
1186 }
1187
1188 // Uncomment this if you want to see all available instructions.
1189 // @todo This doesn't actually work anymore, we should fix it.
1190// printAvailableInsts();
1191
1192 // Execute/writeback any instructions that are available.
1193 int insts_to_execute = fromIssue->size;
1194 int inst_num = 0;
1195 for (; inst_num < insts_to_execute;
1196 ++inst_num) {
1197
1198 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1199
1200 DynInstPtr inst = instQueue.getInstToExecute();
1201
1202 DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n",
1203 inst->pcState(), inst->threadNumber,inst->seqNum);
1204
1205 // Notify potential listeners that this instruction has started
1206 // executing
1207 ppExecute->notify(inst);
1208
1209 // Check if the instruction is squashed; if so then skip it
1210 if (inst->isSquashed()) {
1211 DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]"
1212 " [sn:%i]\n", inst->pcState(), inst->threadNumber,
1213 inst->seqNum);
1214
1215 // Consider this instruction executed so that commit can go
1216 // ahead and retire the instruction.
1217 inst->setExecuted();
1218
1219 // Not sure if I should set this here or just let commit try to
1220 // commit any squashed instructions. I like the latter a bit more.
1221 inst->setCanCommit();
1222
1223 ++iewExecSquashedInsts;
1224
1225 continue;
1226 }
1227
1228 Fault fault = NoFault;
1229
1230 // Execute instruction.
1231 // Note that if the instruction faults, it will be handled
1232 // at the commit stage.
1233 if (inst->isMemRef()) {
1234 DPRINTF(IEW, "Execute: Calculating address for memory "
1235 "reference.\n");
1236
1237 // Tell the LDSTQ to execute this instruction (if it is a load).
1238 if (inst->isLoad()) {
1239 // Loads will mark themselves as executed, and their writeback
1240 // event adds the instruction to the queue to commit
1241 fault = ldstQueue.executeLoad(inst);
1242
1243 if (inst->isTranslationDelayed() &&
1244 fault == NoFault) {
1245 // A hw page table walk is currently going on; the
1246 // instruction must be deferred.
1247 DPRINTF(IEW, "Execute: Delayed translation, deferring "
1248 "load.\n");
1249 instQueue.deferMemInst(inst);
1250 continue;
1251 }
1252
1253 if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
1254 inst->fault = NoFault;
1255 }
1256 } else if (inst->isStore()) {
1257 fault = ldstQueue.executeStore(inst);
1258
1259 if (inst->isTranslationDelayed() &&
1260 fault == NoFault) {
1261 // A hw page table walk is currently going on; the
1262 // instruction must be deferred.
1263 DPRINTF(IEW, "Execute: Delayed translation, deferring "
1264 "store.\n");
1265 instQueue.deferMemInst(inst);
1266 continue;
1267 }
1268
1269 // If the store had a fault then it may not have a mem req
1270 if (fault != NoFault || !inst->readPredicate() ||
1271 !inst->isStoreConditional()) {
1272 // If the instruction faulted, then we need to send it along
1273 // to commit without the instruction completing.
1274 // Send this instruction to commit, also make sure iew stage
1275 // realizes there is activity.
1276 inst->setExecuted();
1277 instToCommit(inst);
1278 activityThisCycle();
1279 }
1280
1281 // Store conditionals will mark themselves as
1282 // executed, and their writeback event will add the
1283 // instruction to the queue to commit.
1284 } else {
1285 panic("Unexpected memory type!\n");
1286 }
1287
1288 } else {
1289 // If the instruction has already faulted, then skip executing it.
1290 // Such case can happen when it faulted during ITLB translation.
1291 // If we execute the instruction (even if it's a nop) the fault
1292 // will be replaced and we will lose it.
1293 if (inst->getFault() == NoFault) {
1294 inst->execute();
1295 if (!inst->readPredicate())
1296 inst->forwardOldRegs();
1297 }
1298
1299 inst->setExecuted();
1300
1301 instToCommit(inst);
1302 }
1303
1304 updateExeInstStats(inst);
1305
1306 // Check if branch prediction was correct, if not then we need
1307 // to tell commit to squash in flight instructions. Only
1308 // handle this if there hasn't already been something that
1309 // redirects fetch in this group of instructions.
1310
1311 // This probably needs to prioritize the redirects if a different
1312 // scheduler is used. Currently the scheduler schedules the oldest
1313 // instruction first, so the branch resolution order will be correct.
1314 ThreadID tid = inst->threadNumber;
1315
1316 if (!fetchRedirect[tid] ||
1317 !toCommit->squash[tid] ||
1318 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1319
1320 // Prevent testing for misprediction on load instructions,
1321 // that have not been executed.
1322 bool loadNotExecuted = !inst->isExecuted() && inst->isLoad();
1323
1324 if (inst->mispredicted() && !loadNotExecuted) {
1325 fetchRedirect[tid] = true;
1326
1327 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1328 DPRINTF(IEW, "Predicted target was PC: %s.\n",
1329 inst->readPredTarg());
1330 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
1331 inst->pcState());
1332 // If incorrect, then signal the ROB that it must be squashed.
1333 squashDueToBranch(inst, tid);
1334
1335 ppMispredict->notify(inst);
1336
1337 if (inst->readPredTaken()) {
1338 predictedTakenIncorrect++;
1339 } else {
1340 predictedNotTakenIncorrect++;
1341 }
1342 } else if (ldstQueue.violation(tid)) {
1343 assert(inst->isMemRef());
1344 // If there was an ordering violation, then get the
1345 // DynInst that caused the violation. Note that this
1346 // clears the violation signal.
1347 DynInstPtr violator;
1348 violator = ldstQueue.getMemDepViolator(tid);
1349
1350 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s "
1351 "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n",
1352 violator->pcState(), violator->seqNum,
1353 inst->pcState(), inst->seqNum, inst->physEffAddrLow);
1354
1355 fetchRedirect[tid] = true;
1356
1357 // Tell the instruction queue that a violation has occured.
1358 instQueue.violation(inst, violator);
1359
1360 // Squash.
1361 squashDueToMemOrder(violator, tid);
1362
1363 ++memOrderViolationEvents;
1364 }
1365 } else {
1366 // Reset any state associated with redirects that will not
1367 // be used.
1368 if (ldstQueue.violation(tid)) {
1369 assert(inst->isMemRef());
1370
1371 DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1372
1373 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1374 "%s, inst PC: %s. Addr is: %#x.\n",
1375 violator->pcState(), inst->pcState(),
1376 inst->physEffAddrLow);
1377 DPRINTF(IEW, "Violation will not be handled because "
1378 "already squashing\n");
1379
1380 ++memOrderViolationEvents;
1381 }
1382 }
1383 }
1384
1385 // Update and record activity if we processed any instructions.
1386 if (inst_num) {
1387 if (exeStatus == Idle) {
1388 exeStatus = Running;
1389 }
1390
1391 updatedQueues = true;
1392
1393 cpu->activityThisCycle();
1394 }
1395
1396 // Need to reset this in case a writeback event needs to write into the
1397 // iew queue. That way the writeback event will write into the correct
1398 // spot in the queue.
1399 wbNumInst = 0;
1400
1401}
1402
1403template <class Impl>
1404void
1405DefaultIEW<Impl>::writebackInsts()
1406{
1407 // Loop through the head of the time buffer and wake any
1408 // dependents. These instructions are about to write back. Also
1409 // mark scoreboard that this instruction is finally complete.
1410 // Either have IEW have direct access to scoreboard, or have this
1411 // as part of backwards communication.
1412 for (int inst_num = 0; inst_num < wbWidth &&
1413 toCommit->insts[inst_num]; inst_num++) {
1414 DynInstPtr inst = toCommit->insts[inst_num];
1415 ThreadID tid = inst->threadNumber;
1416
1417 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n",
1418 inst->seqNum, inst->pcState());
1419
1420 iewInstsToCommit[tid]++;
1421 // Notify potential listeners that execution is complete for this
1422 // instruction.
1423 ppToCommit->notify(inst);
1424
1425 // Some instructions will be sent to commit without having
1426 // executed because they need commit to handle them.
1427 // E.g. Strictly ordered loads have not actually executed when they
1428 // are first sent to commit. Instead commit must tell the LSQ
1429 // when it's ready to execute the strictly ordered load.
1430 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1431 int dependents = instQueue.wakeDependents(inst);
1432
1433 for (int i = 0; i < inst->numDestRegs(); i++) {
1434 //mark as Ready
1435 DPRINTF(IEW,"Setting Destination Register %i\n",
1436 inst->renamedDestRegIdx(i));
1437 scoreboard->setReg(inst->renamedDestRegIdx(i));
1438 }
1439
1440 if (dependents) {
1441 producerInst[tid]++;
1442 consumerInst[tid]+= dependents;
1443 }
1444 writebackCount[tid]++;
1445 }
1446 }
1447}
1448
1449template<class Impl>
1450void
1451DefaultIEW<Impl>::tick()
1452{
1453 wbNumInst = 0;
1454 wbCycle = 0;
1455
1456 wroteToTimeBuffer = false;
1457 updatedQueues = false;
1458
1459 sortInsts();
1460
1461 // Free function units marked as being freed this cycle.
1462 fuPool->processFreeUnits();
1463
1464 list<ThreadID>::iterator threads = activeThreads->begin();
1465 list<ThreadID>::iterator end = activeThreads->end();
1466
1467 // Check stall and squash signals, dispatch any instructions.
1468 while (threads != end) {
1469 ThreadID tid = *threads++;
1470
1471 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1472
1473 checkSignalsAndUpdate(tid);
1474 dispatch(tid);
1475 }
1476
1477 if (exeStatus != Squashing) {
1478 executeInsts();
1479
1480 writebackInsts();
1481
1482 // Have the instruction queue try to schedule any ready instructions.
1483 // (In actuality, this scheduling is for instructions that will
1484 // be executed next cycle.)
1485 instQueue.scheduleReadyInsts();
1486
1487 // Also should advance its own time buffers if the stage ran.
1488 // Not the best place for it, but this works (hopefully).
1489 issueToExecQueue.advance();
1490 }
1491
1492 bool broadcast_free_entries = false;
1493
1494 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1495 exeStatus = Idle;
1496 updateLSQNextCycle = false;
1497
1498 broadcast_free_entries = true;
1499 }
1500
1501 // Writeback any stores using any leftover bandwidth.
1502 ldstQueue.writebackStores();
1503
1504 // Check the committed load/store signals to see if there's a load
1505 // or store to commit. Also check if it's being told to execute a
1506 // nonspeculative instruction.
1507 // This is pretty inefficient...
1508
1509 threads = activeThreads->begin();
1510 while (threads != end) {
1511 ThreadID tid = (*threads++);
1512
1513 DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1514
1515 // Update structures based on instructions committed.
1516 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1517 !fromCommit->commitInfo[tid].squash &&
1518 !fromCommit->commitInfo[tid].robSquashing) {
1519
1520 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1521
1522 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1523
1524 updateLSQNextCycle = true;
1525 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1526 }
1527
1528 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1529
1530 //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1531 if (fromCommit->commitInfo[tid].strictlyOrdered) {
1532 instQueue.replayMemInst(
1533 fromCommit->commitInfo[tid].strictlyOrderedLoad);
1534 fromCommit->commitInfo[tid].strictlyOrderedLoad->setAtCommit();
1535 } else {
1536 instQueue.scheduleNonSpec(
1537 fromCommit->commitInfo[tid].nonSpecSeqNum);
1538 }
1539 }
1540
1541 if (broadcast_free_entries) {
1542 toFetch->iewInfo[tid].iqCount =
1543 instQueue.getCount(tid);
1544 toFetch->iewInfo[tid].ldstqCount =
1545 ldstQueue.getCount(tid);
1546
1547 toRename->iewInfo[tid].usedIQ = true;
1548 toRename->iewInfo[tid].freeIQEntries =
1549 instQueue.numFreeEntries(tid);
1550 toRename->iewInfo[tid].usedLSQ = true;
1551
1552 toRename->iewInfo[tid].freeLQEntries =
1553 ldstQueue.numFreeLoadEntries(tid);
1554 toRename->iewInfo[tid].freeSQEntries =
1555 ldstQueue.numFreeStoreEntries(tid);
1556
1557 wroteToTimeBuffer = true;
1558 }
1559
1560 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1561 tid, toRename->iewInfo[tid].dispatched);
1562 }
1563
1564 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). "
1565 "LQ has %i free entries. SQ has %i free entries.\n",
1566 instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1567 ldstQueue.numFreeLoadEntries(), ldstQueue.numFreeStoreEntries());
1568
1569 updateStatus();
1570
1571 if (wroteToTimeBuffer) {
1572 DPRINTF(Activity, "Activity this cycle.\n");
1573 cpu->activityThisCycle();
1574 }
1575}
1576
1577template <class Impl>
1578void
1579DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1580{
1581 ThreadID tid = inst->threadNumber;
1582
1583 iewExecutedInsts++;
1584
1585#if TRACING_ON
1586 if (DTRACE(O3PipeView)) {
1587 inst->completeTick = curTick() - inst->fetchTick;
1588 }
1589#endif
1590
1591 //
1592 // Control operations
1593 //
1594 if (inst->isControl())
1595 iewExecutedBranches[tid]++;
1596
1597 //
1598 // Memory operations
1599 //
1600 if (inst->isMemRef()) {
1601 iewExecutedRefs[tid]++;
1602
1603 if (inst->isLoad()) {
1604 iewExecLoadInsts[tid]++;
1605 }
1606 }
1607}
1608
1609template <class Impl>
1610void
1611DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
1612{
1613 ThreadID tid = inst->threadNumber;
1614
1615 if (!fetchRedirect[tid] ||
1616 !toCommit->squash[tid] ||
1617 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1618
1619 if (inst->mispredicted()) {
1620 fetchRedirect[tid] = true;
1621
1622 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1623 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1624 inst->predInstAddr(), inst->predNextInstAddr());
1625 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
1626 " NPC: %#x.\n", inst->nextInstAddr(),
1627 inst->nextInstAddr());
1628 // If incorrect, then signal the ROB that it must be squashed.
1629 squashDueToBranch(inst, tid);
1630
1631 if (inst->readPredTaken()) {
1632 predictedTakenIncorrect++;
1633 } else {
1634 predictedNotTakenIncorrect++;
1635 }
1636 }
1637 }
1638}
1639
1640#endif//__CPU_O3_IEW_IMPL_IMPL_HH__