1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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447
448template<class Impl>
449void
450DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
451{
452 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
453 "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
454
455 toCommit->squash[tid] = true;
456 toCommit->squashedSeqNum[tid] = inst->seqNum;
457 toCommit->mispredPC[tid] = inst->instAddr();
458 toCommit->branchMispredict[tid] = true;
459 toCommit->mispredictInst[tid] = inst;
460
461 toCommit->branchTaken[tid] = inst->pcState().branching();
462 TheISA::PCState pc = inst->pcState();
463 TheISA::advancePC(pc, inst->staticInst);
464 toCommit->pc[tid] = pc;
465
466 toCommit->includeSquashInst[tid] = false;
467
468 wroteToTimeBuffer = true;
469}
470
471template<class Impl>
472void
473DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
474{
475 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
476 "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
477
478 toCommit->squash[tid] = true;
479 toCommit->squashedSeqNum[tid] = inst->seqNum;
480 TheISA::PCState pc = inst->pcState();
481 TheISA::advancePC(pc, inst->staticInst);
482 toCommit->pc[tid] = pc;
483 toCommit->branchMispredict[tid] = false;
484
485 toCommit->includeSquashInst[tid] = false;
486
487 wroteToTimeBuffer = true;
488}
489
490template<class Impl>
491void
492DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
493{
494 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
495 "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
496
497 toCommit->squash[tid] = true;
498 toCommit->squashedSeqNum[tid] = inst->seqNum;
499 toCommit->pc[tid] = inst->pcState();
500 toCommit->branchMispredict[tid] = false;
501
502 // Must include the broadcasted SN in the squash.
503 toCommit->includeSquashInst[tid] = true;
504
505 ldstQueue.setLoadBlockedHandled(tid);
506
507 wroteToTimeBuffer = true;
508}
509
510template<class Impl>
511void
512DefaultIEW<Impl>::block(ThreadID tid)
513{
514 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
515

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783
784 if (dispatchStatus[tid] == Blocked ||
785 dispatchStatus[tid] == Unblocking) {
786 toRename->iewUnblock[tid] = true;
787 wroteToTimeBuffer = true;
788 }
789
790 dispatchStatus[tid] = Squashing;
791
792 fetchRedirect[tid] = false;
793 return;
794 }
795
796 if (fromCommit->commitInfo[tid].robSquashing) {
797 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
798
799 dispatchStatus[tid] = Squashing;
800
801 emptyRenameInsts(tid);
802 wroteToTimeBuffer = true;
803 return;
804 }
805
806 if (checkStall(tid)) {
807 block(tid);
808 dispatchStatus[tid] = Blocked;

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1281 // redirects fetch in this group of instructions.
1282
1283 // This probably needs to prioritize the redirects if a different
1284 // scheduler is used. Currently the scheduler schedules the oldest
1285 // instruction first, so the branch resolution order will be correct.
1286 ThreadID tid = inst->threadNumber;
1287
1288 if (!fetchRedirect[tid] ||
1289 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1290
1291 if (inst->mispredicted()) {
1292 fetchRedirect[tid] = true;
1293
1294 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1295 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1296 inst->predInstAddr(), inst->predNextInstAddr());

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1377
1378 cpu->activityThisCycle();
1379 }
1380
1381 // Need to reset this in case a writeback event needs to write into the
1382 // iew queue. That way the writeback event will write into the correct
1383 // spot in the queue.
1384 wbNumInst = 0;
1385}
1386
1387template <class Impl>
1388void
1389DefaultIEW<Impl>::writebackInsts()
1390{
1391 // Loop through the head of the time buffer and wake any
1392 // dependents. These instructions are about to write back. Also

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1591
1592template <class Impl>
1593void
1594DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
1595{
1596 ThreadID tid = inst->threadNumber;
1597
1598 if (!fetchRedirect[tid] ||
1599 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1600
1601 if (inst->mispredicted()) {
1602 fetchRedirect[tid] = true;
1603
1604 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1605 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1606 inst->predInstAddr(), inst->predNextInstAddr());

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