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1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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1148 }
1149
1150 toRename->iewInfo[tid].dispatchedToLSQ++;
1151 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1152 // Same as non-speculative stores.
1153 inst->setCanCommit();
1154 instQueue.insertBarrier(inst);
1155 add_to_iq = false;
1156 } else if (inst->isNonSpeculative()) {
1157 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1158 "encountered, skipping.\n", tid);
1159
1160 // Same as non-speculative stores.
1161 inst->setCanCommit();
1162
1163 // Specifically insert it as nonspeculative.
1164 instQueue.insertNonSpec(inst);
1165
1166 ++iewDispNonSpecInsts;
1167
1168 add_to_iq = false;
1169 } else if (inst->isNop()) {
1170 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1171 "skipping.\n", tid);
1172
1173 inst->setIssued();
1174 inst->setExecuted();
1175 inst->setCanCommit();
1176

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1188 inst->setCanCommit();
1189
1190 instQueue.recordProducer(inst);
1191
1192 add_to_iq = false;
1193 } else {
1194 add_to_iq = true;
1195 }
1196
1197 // If the instruction queue is not full, then add the
1198 // instruction.
1199 if (add_to_iq) {
1200 instQueue.insert(inst);
1201 }
1202
1203 insts_to_dispatch.pop();
1204

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1374 squashDueToBranch(inst, tid);
1375
1376 if (inst->readPredTaken()) {
1377 predictedTakenIncorrect++;
1378 } else {
1379 predictedNotTakenIncorrect++;
1380 }
1381 } else if (ldstQueue.violation(tid)) {
1382 // If there was an ordering violation, then get the
1383 // DynInst that caused the violation. Note that this
1384 // clears the violation signal.
1385 DynInstPtr violator;
1386 violator = ldstQueue.getMemDepViolator(tid);
1387
1388 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1389 "%#x, inst PC: %#x. Addr is: %#x.\n",
1390 violator->readPC(), inst->readPC(), inst->physEffAddr);
1391
1392 // Ensure the violating instruction is older than
1393 // current squash
1394 if (fetchRedirect[tid] &&
1395 violator->seqNum >= toCommit->squashedSeqNum[tid])
1396 continue;
1397
1398 fetchRedirect[tid] = true;
1399
1400 // Tell the instruction queue that a violation has occured.
1401 instQueue.violation(inst, violator);
1402
1403 // Squash.
1404 squashDueToMemOrder(inst,tid);
1405
1406 ++memOrderViolationEvents;
1407 } else if (ldstQueue.loadBlocked(tid) &&
1408 !ldstQueue.isLoadBlockedHandled(tid)) {
1409 fetchRedirect[tid] = true;
1410
1411 DPRINTF(IEW, "Load operation couldn't execute because the "
1412 "memory system is blocked. PC: %#x [sn:%lli]\n",
1413 inst->readPC(), inst->seqNum);
1414
1415 squashDueToMemBlocked(inst, tid);
1416 }
1417 }
1418 }
1419
1420 // Update and record activity if we processed any instructions.
1421 if (inst_num) {
1422 if (exeStatus == Idle) {
1423 exeStatus = Running;
1424 }

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1558 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1559 }
1560
1561 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1562
1563 //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1564 if (fromCommit->commitInfo[tid].uncached) {
1565 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1566 } else {
1567 instQueue.scheduleNonSpec(
1568 fromCommit->commitInfo[tid].nonSpecSeqNum);
1569 }
1570 }
1571
1572 if (broadcast_free_entries) {
1573 toFetch->iewInfo[tid].iqCount =

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