1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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476 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
477
478 toCommit->squash[tid] = true;
479 toCommit->squashedSeqNum[tid] = inst->seqNum;
480 toCommit->mispredPC[tid] = inst->readPC();
481 toCommit->branchMispredict[tid] = true;
482
483#if ISA_HAS_DELAY_SLOT
484 bool branch_taken = inst->readNextNPC() !=
485 (inst->readNextPC() + sizeof(TheISA::MachInst));
486
487 toCommit->branchTaken[tid] = branch_taken;
488
489 toCommit->condDelaySlotBranch[tid] = inst->isCondDelaySlot();
490
491 if (inst->isCondDelaySlot() && branch_taken) {
492 toCommit->nextPC[tid] = inst->readNextPC();
493 } else {
494 toCommit->nextPC[tid] = inst->readNextNPC();
495 }
496#else
497 toCommit->branchTaken[tid] = inst->readNextPC() !=
498 (inst->readPC() + sizeof(TheISA::MachInst));
499 toCommit->nextPC[tid] = inst->readNextPC();
500#endif
501
502 toCommit->includeSquashInst[tid] = false;
503

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509DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
510{
511 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
512 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
513
514 toCommit->squash[tid] = true;
515 toCommit->squashedSeqNum[tid] = inst->seqNum;
516 toCommit->nextPC[tid] = inst->readNextPC();
517 toCommit->branchMispredict[tid] = false;
518
519 toCommit->includeSquashInst[tid] = false;
520
521 wroteToTimeBuffer = true;
522}
523
524template<class Impl>
525void
526DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
527{
528 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
529 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
530
531 toCommit->squash[tid] = true;
532 toCommit->squashedSeqNum[tid] = inst->seqNum;
533 toCommit->nextPC[tid] = inst->readPC();
534 toCommit->branchMispredict[tid] = false;
535
536 // Must include the broadcasted SN in the squash.
537 toCommit->includeSquashInst[tid] = true;
538
539 ldstQueue.setLoadBlockedHandled(tid);
540
541 wroteToTimeBuffer = true;

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666}
667
668template<class Impl>
669int
670DefaultIEW<Impl>::skidCount()
671{
672 int max=0;
673
674 std::list<unsigned>::iterator threads = activeThreads->begin();
675 std::list<unsigned>::iterator end = activeThreads->end();
676
677 while (threads != end) {
678 unsigned tid = *threads++;
679 unsigned thread_count = skidBuffer[tid].size();
680 if (max < thread_count)
681 max = thread_count;
682 }
683
684 return max;
685}
686
687template<class Impl>
688bool
689DefaultIEW<Impl>::skidsEmpty()
690{
691 std::list<unsigned>::iterator threads = activeThreads->begin();
692 std::list<unsigned>::iterator end = activeThreads->end();
693
694 while (threads != end) {
695 unsigned tid = *threads++;
696
697 if (!skidBuffer[tid].empty())
698 return false;
699 }
700
701 return true;
702}
703
704template <class Impl>
705void
706DefaultIEW<Impl>::updateStatus()
707{
708 bool any_unblocking = false;
709
710 std::list<unsigned>::iterator threads = activeThreads->begin();
711 std::list<unsigned>::iterator end = activeThreads->end();
712
713 while (threads != end) {
714 unsigned tid = *threads++;
715
716 if (dispatchStatus[tid] == Unblocking) {
717 any_unblocking = true;
718 break;
719 }
720 }
721

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1119 add_to_iq = false;
1120
1121 ++iewDispNonSpecInsts;
1122 } else {
1123 add_to_iq = true;
1124 }
1125
1126 toRename->iewInfo[tid].dispatchedToLSQ++;
1127 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1128 // Same as non-speculative stores.
1129 inst->setCanCommit();
1130 instQueue.insertBarrier(inst);
1131 add_to_iq = false;
1132 } else if (inst->isNonSpeculative()) {
1133 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1134 "encountered, skipping.\n", tid);
1135
1136 // Same as non-speculative stores.
1137 inst->setCanCommit();
1138
1139 // Specifically insert it as nonspeculative.

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1223
1224template <class Impl>
1225void
1226DefaultIEW<Impl>::executeInsts()
1227{
1228 wbNumInst = 0;
1229 wbCycle = 0;
1230
1231 std::list<unsigned>::iterator threads = activeThreads->begin();
1232 std::list<unsigned>::iterator end = activeThreads->end();
1233
1234 while (threads != end) {
1235 unsigned tid = *threads++;
1236 fetchRedirect[tid] = false;
1237 }
1238
1239 // Uncomment this if you want to see all available instructions.
1240// printAvailableInsts();
1241
1242 // Execute/writeback any instructions that are available.

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1336
1337 if (!fetchRedirect[tid] ||
1338 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1339
1340 if (inst->mispredicted()) {
1341 fetchRedirect[tid] = true;
1342
1343 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1344#if ISA_HAS_DELAY_SLOT
1345 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1346 inst->nextNPC);
1347#else
1348 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1349 inst->nextPC);
1350#endif
1351 // If incorrect, then signal the ROB that it must be squashed.
1352 squashDueToBranch(inst, tid);
1353
1354 if (inst->predTaken()) {
1355 predictedTakenIncorrect++;
1356 } else {
1357 predictedNotTakenIncorrect++;
1358 }
1359 } else if (ldstQueue.violation(tid)) {
1360 // If there was an ordering violation, then get the
1361 // DynInst that caused the violation. Note that this
1362 // clears the violation signal.

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1467 wroteToTimeBuffer = false;
1468 updatedQueues = false;
1469
1470 sortInsts();
1471
1472 // Free function units marked as being freed this cycle.
1473 fuPool->processFreeUnits();
1474
1475 std::list<unsigned>::iterator threads = activeThreads->begin();
1476 std::list<unsigned>::iterator end = activeThreads->end();
1477
1478 // Check stall and squash signals, dispatch any instructions.
1479 while (threads != end) {
1480 unsigned tid = *threads++;
1481
1482 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1483
1484 checkSignalsAndUpdate(tid);
1485 dispatch(tid);
1486 }
1487
1488 if (exeStatus != Squashing) {

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1512 // Writeback any stores using any leftover bandwidth.
1513 ldstQueue.writebackStores();
1514
1515 // Check the committed load/store signals to see if there's a load
1516 // or store to commit. Also check if it's being told to execute a
1517 // nonspeculative instruction.
1518 // This is pretty inefficient...
1519
1520 threads = activeThreads->begin();
1521 while (threads != end) {
1522 unsigned tid = (*threads++);
1523
1524 DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1525
1526 // Update structures based on instructions committed.
1527 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1528 !fromCommit->commitInfo[tid].squash &&
1529 !fromCommit->commitInfo[tid].robSquashing) {

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