1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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476 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
477
478 toCommit->squash[tid] = true;
479 toCommit->squashedSeqNum[tid] = inst->seqNum;
480 toCommit->mispredPC[tid] = inst->readPC();
481 toCommit->branchMispredict[tid] = true;
482
483#if ISA_HAS_DELAY_SLOT
484 int instSize = sizeof(TheISA::MachInst);
485 bool branch_taken =
486 !(inst->readNextPC() + instSize == inst->readNextNPC() &&
487 (inst->readNextPC() == inst->readPC() + instSize ||
488 inst->readNextPC() == inst->readPC() + 2 * instSize));
489 DPRINTF(Sparc, "Branch taken = %s [sn:%i]\n",
490 branch_taken ? "true": "false", inst->seqNum);
491
492 toCommit->branchTaken[tid] = branch_taken;
493
494 bool squashDelaySlot = true;
495// (inst->readNextPC() != inst->readPC() + sizeof(TheISA::MachInst));
496 DPRINTF(Sparc, "Squash delay slot = %s [sn:%i]\n",
497 squashDelaySlot ? "true": "false", inst->seqNum);
498 toCommit->squashDelaySlot[tid] = squashDelaySlot;
499 //If we're squashing the delay slot, we need to pick back up at NextPC.
500 //Otherwise, NextPC isn't being squashed, so we should pick back up at
501 //NextNPC.
502 if (squashDelaySlot) {
503 toCommit->nextPC[tid] = inst->readNextPC();
504 toCommit->nextNPC[tid] = inst->readNextNPC();
505 } else
506 toCommit->nextPC[tid] = inst->readNextNPC();
507#else
508 toCommit->branchTaken[tid] = inst->readNextPC() !=
509 (inst->readPC() + sizeof(TheISA::MachInst));
510 toCommit->nextPC[tid] = inst->readNextPC();
511#endif
512
513 toCommit->includeSquashInst[tid] = false;
514

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520DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
521{
522 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
523 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
524
525 toCommit->squash[tid] = true;
526 toCommit->squashedSeqNum[tid] = inst->seqNum;
527 toCommit->nextPC[tid] = inst->readNextPC();
528#if ISA_HAS_DELAY_SLOT
529 toCommit->nextNPC[tid] = inst->readNextNPC();
530#endif
531
532 toCommit->includeSquashInst[tid] = false;
533
534 wroteToTimeBuffer = true;
535}
536
537template<class Impl>
538void
539DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
540{
541 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
542 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
543
544 toCommit->squash[tid] = true;
545 toCommit->squashedSeqNum[tid] = inst->seqNum;
546 toCommit->nextPC[tid] = inst->readPC();
547#if ISA_HAS_DELAY_SLOT
548 toCommit->nextNPC[tid] = inst->readNextNPC();
549#endif
550
551 // Must include the broadcasted SN in the squash.
552 toCommit->includeSquashInst[tid] = true;
553
554 ldstQueue.setLoadBlockedHandled(tid);
555
556 wroteToTimeBuffer = true;
557}

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681}
682
683template<class Impl>
684int
685DefaultIEW<Impl>::skidCount()
686{
687 int max=0;
688
689 std::list<unsigned>::iterator threads = (*activeThreads).begin();
690
691 while (threads != (*activeThreads).end()) {
692 unsigned thread_count = skidBuffer[*threads++].size();
693 if (max < thread_count)
694 max = thread_count;
695 }
696
697 return max;
698}
699
700template<class Impl>
701bool
702DefaultIEW<Impl>::skidsEmpty()
703{
704 std::list<unsigned>::iterator threads = (*activeThreads).begin();
705
706 while (threads != (*activeThreads).end()) {
707 if (!skidBuffer[*threads++].empty())
708 return false;
709 }
710
711 return true;
712}
713
714template <class Impl>
715void
716DefaultIEW<Impl>::updateStatus()
717{
718 bool any_unblocking = false;
719
720 std::list<unsigned>::iterator threads = (*activeThreads).begin();
721
722 threads = (*activeThreads).begin();
723
724 while (threads != (*activeThreads).end()) {
725 unsigned tid = *threads++;
726
727 if (dispatchStatus[tid] == Unblocking) {
728 any_unblocking = true;
729 break;
730 }
731 }
732

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1236
1237template <class Impl>
1238void
1239DefaultIEW<Impl>::executeInsts()
1240{
1241 wbNumInst = 0;
1242 wbCycle = 0;
1243
1244 std::list<unsigned>::iterator threads = (*activeThreads).begin();
1245
1246 while (threads != (*activeThreads).end()) {
1247 unsigned tid = *threads++;
1248 fetchRedirect[tid] = false;
1249 }
1250
1251 // Uncomment this if you want to see all available instructions.
1252// printAvailableInsts();
1253
1254 // Execute/writeback any instructions that are available.

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1303 // If the store had a fault then it may not have a mem req
1304 if (!inst->isStoreConditional() && fault == NoFault) {
1305 inst->setExecuted();
1306
1307 instToCommit(inst);
1308 } else if (fault != NoFault) {
1309 // If the instruction faulted, then we need to send it along to commit
1310 // without the instruction completing.
1311 DPRINTF(IEW, "Store has fault! [sn:%lli]\n", inst->seqNum);
1312
1313 // Send this instruction to commit, also make sure iew stage
1314 // realizes there is activity.
1315 inst->setExecuted();
1316
1317 instToCommit(inst);
1318 activityThisCycle();
1319 }

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1340 // handle this if there hasn't already been something that
1341 // redirects fetch in this group of instructions.
1342
1343 // This probably needs to prioritize the redirects if a different
1344 // scheduler is used. Currently the scheduler schedules the oldest
1345 // instruction first, so the branch resolution order will be correct.
1346 unsigned tid = inst->threadNumber;
1347
1348 if (!fetchRedirect[tid]) {
1349
1350 if (inst->mispredicted()) {
1351 fetchRedirect[tid] = true;
1352
1353 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1354 DPRINTF(IEW, "Predicted target was %#x.\n", inst->predPC);
1355#if ISA_HAS_DELAY_SLOT
1356 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1357 inst->nextNPC);
1358#else
1359 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1360 inst->nextPC);
1361#endif
1362 // If incorrect, then signal the ROB that it must be squashed.
1363 squashDueToBranch(inst, tid);
1364
1365 if (inst->readPredTaken()) {
1366 predictedTakenIncorrect++;
1367 } else {
1368 predictedNotTakenIncorrect++;
1369 }
1370 } else if (ldstQueue.violation(tid)) {
1371 fetchRedirect[tid] = true;
1372
1373 // If there was an ordering violation, then get the
1374 // DynInst that caused the violation. Note that this
1375 // clears the violation signal.
1376 DynInstPtr violator;
1377 violator = ldstQueue.getMemDepViolator(tid);
1378
1379 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1380 "%#x, inst PC: %#x. Addr is: %#x.\n",
1381 violator->readPC(), inst->readPC(), inst->physEffAddr);
1382
1383 // Tell the instruction queue that a violation has occured.
1384 instQueue.violation(inst, violator);
1385
1386 // Squash.
1387 squashDueToMemOrder(inst,tid);
1388
1389 ++memOrderViolationEvents;
1390 } else if (ldstQueue.loadBlocked(tid) &&

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1472 wroteToTimeBuffer = false;
1473 updatedQueues = false;
1474
1475 sortInsts();
1476
1477 // Free function units marked as being freed this cycle.
1478 fuPool->processFreeUnits();
1479
1480 std::list<unsigned>::iterator threads = (*activeThreads).begin();
1481
1482 // Check stall and squash signals, dispatch any instructions.
1483 while (threads != (*activeThreads).end()) {
1484 unsigned tid = *threads++;
1485
1486 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1487
1488 checkSignalsAndUpdate(tid);
1489 dispatch(tid);
1490 }
1491
1492 if (exeStatus != Squashing) {

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1516 // Writeback any stores using any leftover bandwidth.
1517 ldstQueue.writebackStores();
1518
1519 // Check the committed load/store signals to see if there's a load
1520 // or store to commit. Also check if it's being told to execute a
1521 // nonspeculative instruction.
1522 // This is pretty inefficient...
1523
1524 threads = (*activeThreads).begin();
1525 while (threads != (*activeThreads).end()) {
1526 unsigned tid = (*threads++);
1527
1528 DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1529
1530 // Update structures based on instructions committed.
1531 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1532 !fromCommit->commitInfo[tid].squash &&
1533 !fromCommit->commitInfo[tid].robSquashing) {

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