1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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157
158 branchMispredicts
159 .name(name() + ".branchMispredicts")
160 .desc("Number of branch mispredicts detected at execute");
161
162 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
163
164 iewExecutedInsts
165 .name(name() + ".EXEC:insts")
166 .desc("Number of executed instructions");
167
168 iewExecLoadInsts
169 .init(cpu->number_of_threads)
170 .name(name() + ".EXEC:loads")
171 .desc("Number of load instructions executed")
172 .flags(total);
173
174 iewExecSquashedInsts
175 .name(name() + ".EXEC:squashedInsts")
176 .desc("Number of squashed instructions skipped in execute");
177
178 iewExecutedSwp
179 .init(cpu->number_of_threads)
180 .name(name() + ".EXEC:swp")
181 .desc("number of swp insts executed")
182 .flags(total);
183

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367}
368
369template <class Impl>
370void
371DefaultIEW<Impl>::switchOut()
372{
373 // Clear any state.
374 switchedOut = true;
375
376 instQueue.switchOut();
377 ldstQueue.switchOut();
378 fuPool->switchOut();
379
380 for (int i = 0; i < numThreads; i++) {
381 while (!insts[i].empty())
382 insts[i].pop();

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405 for (int i=0; i < numThreads; i++) {
406 dispatchStatus[i] = Running;
407 stalls[i].commit = false;
408 fetchRedirect[i] = false;
409 }
410
411 updateLSQNextCycle = false;
412
413 // @todo: Fix hardcoded number
414 for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
415 issueToExecQueue.advance();
416 }
417}
418
419template<class Impl>
420void
421DefaultIEW<Impl>::squash(unsigned tid)

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606 // free slot.
607 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
608 ++wbNumInst;
609 if (wbNumInst == wbWidth) {
610 ++wbCycle;
611 wbNumInst = 0;
612 }
613
614 assert((wbCycle * wbWidth + wbNumInst) < wbMax);
615 }
616
617 // Add finished instruction to queue to commit.
618 (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
619 (*iewQueue)[wbCycle].size++;
620}
621
622template <class Impl>
623unsigned
624DefaultIEW<Impl>::validInstsFromRename()

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898 toRename->iewInfo[tid].dispatched++;
899
900 insts[tid].pop();
901 }
902}
903
904template <class Impl>
905void
906DefaultIEW<Impl>::wakeCPU()
907{
908 cpu->wakeCPU();
909}
910
911template <class Impl>
912void
913DefaultIEW<Impl>::activityThisCycle()

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1268 "reference.\n");
1269
1270 // Tell the LDSTQ to execute this instruction (if it is a load).
1271 if (inst->isLoad()) {
1272 // Loads will mark themselves as executed, and their writeback
1273 // event adds the instruction to the queue to commit
1274 fault = ldstQueue.executeLoad(inst);
1275 } else if (inst->isStore()) {
1276 ldstQueue.executeStore(inst);
1277
1278 // If the store had a fault then it may not have a mem req
1279 if (inst->req && !(inst->req->getFlags() & LOCKED)) {
1280 inst->setExecuted();
1281
1282 instToCommit(inst);
1283 }
1284
1285 // Store conditionals will mark themselves as
1286 // executed, and their writeback event will add the
1287 // instruction to the queue to commit.
1288 } else {
1289 panic("Unexpected memory type!\n");
1290 }

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1399
1400 iewInstsToCommit[tid]++;
1401
1402 // Some instructions will be sent to commit without having
1403 // executed because they need commit to handle them.
1404 // E.g. Uncached loads have not actually executed when they
1405 // are first sent to commit. Instead commit must tell the LSQ
1406 // when it's ready to execute the uncached load.
1407 if (!inst->isSquashed() && inst->isExecuted()) {
1408 int dependents = instQueue.wakeDependents(inst);
1409
1410 for (int i = 0; i < inst->numDestRegs(); i++) {
1411 //mark as Ready
1412 DPRINTF(IEW,"Setting Destination Register %i\n",
1413 inst->renamedDestRegIdx(i));
1414 scoreboard->setReg(inst->renamedDestRegIdx(i));
1415 }

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