1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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68
69 instQueue.setIEW(this);
70 ldstQueue.setIEW(this);
71
72 for (int i=0; i < numThreads; i++) {
73 dispatchStatus[i] = Running;
74 stalls[i].commit = false;
75 fetchRedirect[i] = false;
76 }
77
78 wbMax = wbWidth * params->wbDepth;
79
80 updateLSQNextCycle = false;
81
82 ableToIssue = true;
83

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423{
424 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
425 tid);
426
427 // Tell the IQ to start squashing.
428 instQueue.squash(tid);
429
430 // Tell the LDSTQ to start squashing.
431 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
432
433 updatedQueues = true;
434
435 // Clear the skid buffer in case it has any data in it.
436 while (!skidBuffer[tid].empty()) {
437
438 if (skidBuffer[tid].front()->isLoad() ||
439 skidBuffer[tid].front()->isStore() ) {
440 toRename->iewInfo[tid].dispatchedToLSQ++;
441 }
442
443 toRename->iewInfo[tid].dispatched++;
444
445 skidBuffer[tid].pop();
446 }
447
448 emptyRenameInsts(tid);
449}
450
451template<class Impl>
452void
453DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
454{
455 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
456 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
457
458 toCommit->squash[tid] = true;
459 toCommit->squashedSeqNum[tid] = inst->seqNum;
460 toCommit->mispredPC[tid] = inst->readPC();
461 toCommit->nextPC[tid] = inst->readNextPC();
462 toCommit->branchMispredict[tid] = true;
463 toCommit->branchTaken[tid] = inst->readNextPC() !=
464 (inst->readPC() + sizeof(TheISA::MachInst));
465
466 toCommit->includeSquashInst[tid] = false;
467
468 wroteToTimeBuffer = true;
469}
470
471template<class Impl>
472void
473DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)

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820}
821
822template <class Impl>
823void
824DefaultIEW<Impl>::sortInsts()
825{
826 int insts_from_rename = fromRename->size;
827#ifdef DEBUG
828 for (int i = 0; i < numThreads; i++)
829 assert(insts[i].empty());
830#endif
831 for (int i = 0; i < insts_from_rename; ++i) {
832 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
833 }
834}
835
836template <class Impl>
837void
838DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
839{
840 while (!insts[tid].empty()) {
841 if (insts[tid].front()->isLoad() ||
842 insts[tid].front()->isStore() ) {
843 toRename->iewInfo[tid].dispatchedToLSQ++;
844 }
845
846 toRename->iewInfo[tid].dispatched++;
847
848 insts[tid].pop();

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1115 insts_to_dispatch.pop();
1116
1117 toRename->iewInfo[tid].dispatched++;
1118
1119 ++iewDispatchedInsts;
1120 }
1121
1122 if (!insts_to_dispatch.empty()) {
1123 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n");
1124 block(tid);
1125 toRename->iewUnblock[tid] = false;
1126 }
1127
1128 if (dispatchStatus[tid] == Idle && dis_num_inst) {
1129 dispatchStatus[tid] = Running;
1130
1131 updatedQueues = true;

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1258 unsigned tid = inst->threadNumber;
1259
1260 if (!fetchRedirect[tid]) {
1261
1262 if (inst->mispredicted()) {
1263 fetchRedirect[tid] = true;
1264
1265 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1266 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1267 inst->nextPC);
1268
1269 // If incorrect, then signal the ROB that it must be squashed.
1270 squashDueToBranch(inst, tid);
1271
1272 if (inst->predTaken()) {
1273 predictedTakenIncorrect++;
1274 } else {
1275 predictedNotTakenIncorrect++;
1276 }

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