1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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310DefaultIEW<Impl>::startupStage()
311{
312 for (ThreadID tid = 0; tid < numThreads; tid++) {
313 toRename->iewInfo[tid].usedIQ = true;
314 toRename->iewInfo[tid].freeIQEntries =
315 instQueue.numFreeEntries(tid);
316
317 toRename->iewInfo[tid].usedLSQ = true;
318 toRename->iewInfo[tid].freeLSQEntries =
319 ldstQueue.numFreeEntries(tid);
320 }
321
322 // Initialize the checker's dcache port here
323 if (cpu->checker) {
324 cpu->checker->setDcachePort(&cpu->getDataPort());
325 }
326
327 cpu->activateStage(O3CPU::IEWIdx);

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462 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
463 updatedQueues = true;
464
465 // Clear the skid buffer in case it has any data in it.
466 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
467 tid, fromCommit->commitInfo[tid].doneSeqNum);
468
469 while (!skidBuffer[tid].empty()) {
470 if (skidBuffer[tid].front()->isLoad() ||
471 skidBuffer[tid].front()->isStore() ) {
472 toRename->iewInfo[tid].dispatchedToLSQ++;
473 }
474
475 toRename->iewInfo[tid].dispatched++;
476
477 skidBuffer[tid].pop();
478 }
479
480 emptyRenameInsts(tid);
481}

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898template <class Impl>
899void
900DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid)
901{
902 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
903
904 while (!insts[tid].empty()) {
905
906 if (insts[tid].front()->isLoad() ||
907 insts[tid].front()->isStore() ) {
908 toRename->iewInfo[tid].dispatchedToLSQ++;
909 }
910
911 toRename->iewInfo[tid].dispatched++;
912
913 insts[tid].pop();
914 }
915}
916
917template <class Impl>

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1038 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
1039 "not adding to IQ.\n", tid);
1040
1041 ++iewDispSquashedInsts;
1042
1043 insts_to_dispatch.pop();
1044
1045 //Tell Rename That An Instruction has been processed
1046 if (inst->isLoad() || inst->isStore()) {
1047 toRename->iewInfo[tid].dispatchedToLSQ++;
1048 }
1049 toRename->iewInfo[tid].dispatched++;
1050
1051 continue;
1052 }
1053
1054 // Check for full conditions.
1055 if (instQueue.isFull(tid)) {
1056 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);

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1088 // Reserve a spot in the load store queue for this
1089 // memory access.
1090 ldstQueue.insertLoad(inst);
1091
1092 ++iewDispLoadInsts;
1093
1094 add_to_iq = true;
1095
1096 toRename->iewInfo[tid].dispatchedToLSQ++;
1097 } else if (inst->isStore()) {
1098 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1099 "encountered, adding to LSQ.\n", tid);
1100
1101 ldstQueue.insertStore(inst);
1102
1103 ++iewDispStoreInsts;
1104

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1111 instQueue.insertNonSpec(inst);
1112 add_to_iq = false;
1113
1114 ++iewDispNonSpecInsts;
1115 } else {
1116 add_to_iq = true;
1117 }
1118
1119 toRename->iewInfo[tid].dispatchedToLSQ++;
1120 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1121 // Same as non-speculative stores.
1122 inst->setCanCommit();
1123 instQueue.insertBarrier(inst);
1124 add_to_iq = false;
1125 } else if (inst->isNop()) {
1126 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1127 "skipping.\n", tid);

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1608 instQueue.getCount(tid);
1609 toFetch->iewInfo[tid].ldstqCount =
1610 ldstQueue.getCount(tid);
1611
1612 toRename->iewInfo[tid].usedIQ = true;
1613 toRename->iewInfo[tid].freeIQEntries =
1614 instQueue.numFreeEntries(tid);
1615 toRename->iewInfo[tid].usedLSQ = true;
1616 toRename->iewInfo[tid].freeLSQEntries =
1617 ldstQueue.numFreeEntries(tid);
1618
1619 wroteToTimeBuffer = true;
1620 }
1621
1622 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1623 tid, toRename->iewInfo[tid].dispatched);
1624 }
1625
1626 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). "
1627 "LSQ has %i free entries.\n",
1628 instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1629 ldstQueue.numFreeEntries());
1630
1631 updateStatus();
1632
1633 if (wroteToTimeBuffer) {
1634 DPRINTF(Activity, "Activity this cycle.\n");
1635 cpu->activityThisCycle();
1636 }
1637}

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