1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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1148 }
1149
1150 toRename->iewInfo[tid].dispatchedToLSQ++;
1151 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1152 // Same as non-speculative stores.
1153 inst->setCanCommit();
1154 instQueue.insertBarrier(inst);
1155 add_to_iq = false;
1156 } else if (inst->isNop()) {
1157 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1158 "skipping.\n", tid);
1159
1160 inst->setIssued();
1161 inst->setExecuted();
1162 inst->setCanCommit();
1163

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1175 inst->setCanCommit();
1176
1177 instQueue.recordProducer(inst);
1178
1179 add_to_iq = false;
1180 } else {
1181 add_to_iq = true;
1182 }
1183 if (inst->isNonSpeculative()) {
1184 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1185 "encountered, skipping.\n", tid);
1186
1187 // Same as non-speculative stores.
1188 inst->setCanCommit();
1189
1190 // Specifically insert it as nonspeculative.
1191 instQueue.insertNonSpec(inst);
1192
1193 ++iewDispNonSpecInsts;
1194
1195 add_to_iq = false;
1196 }
1197
1198 // If the instruction queue is not full, then add the
1199 // instruction.
1200 if (add_to_iq) {
1201 instQueue.insert(inst);
1202 }
1203
1204 insts_to_dispatch.pop();
1205

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1375 squashDueToBranch(inst, tid);
1376
1377 if (inst->readPredTaken()) {
1378 predictedTakenIncorrect++;
1379 } else {
1380 predictedNotTakenIncorrect++;
1381 }
1382 } else if (ldstQueue.violation(tid)) {
1383 assert(inst->isMemRef());
1384 // If there was an ordering violation, then get the
1385 // DynInst that caused the violation. Note that this
1386 // clears the violation signal.
1387 DynInstPtr violator;
1388 violator = ldstQueue.getMemDepViolator(tid);
1389
1390 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1391 "%#x, inst PC: %#x. Addr is: %#x.\n",
1392 violator->readPC(), inst->readPC(), inst->physEffAddr);
1393
1394 // Ensure the violating instruction is older than
1395 // current squash
1396/* if (fetchRedirect[tid] &&
1397 violator->seqNum >= toCommit->squashedSeqNum[tid] + 1)
1398 continue;
1399*/
1400 fetchRedirect[tid] = true;
1401
1402 // Tell the instruction queue that a violation has occured.
1403 instQueue.violation(inst, violator);
1404
1405 // Squash.
1406 squashDueToMemOrder(inst,tid);
1407
1408 ++memOrderViolationEvents;
1409 } else if (ldstQueue.loadBlocked(tid) &&
1410 !ldstQueue.isLoadBlockedHandled(tid)) {
1411 fetchRedirect[tid] = true;
1412
1413 DPRINTF(IEW, "Load operation couldn't execute because the "
1414 "memory system is blocked. PC: %#x [sn:%lli]\n",
1415 inst->readPC(), inst->seqNum);
1416
1417 squashDueToMemBlocked(inst, tid);
1418 }
1419 } else {
1420 // Reset any state associated with redirects that will not
1421 // be used.
1422 if (ldstQueue.violation(tid)) {
1423 assert(inst->isMemRef());
1424
1425 DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1426
1427 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1428 "%#x, inst PC: %#x. Addr is: %#x.\n",
1429 violator->readPC(), inst->readPC(), inst->physEffAddr);
1430 DPRINTF(IEW, "Violation will not be handled because "
1431 "already squashing\n");
1432
1433 ++memOrderViolationEvents;
1434 }
1435 if (ldstQueue.loadBlocked(tid) &&
1436 !ldstQueue.isLoadBlockedHandled(tid)) {
1437 DPRINTF(IEW, "Load operation couldn't execute because the "
1438 "memory system is blocked. PC: %#x [sn:%lli]\n",
1439 inst->readPC(), inst->seqNum);
1440 DPRINTF(IEW, "Blocked load will not be handled because "
1441 "already squashing\n");
1442
1443 ldstQueue.setLoadBlockedHandled(tid);
1444 }
1445
1446 }
1447 }
1448
1449 // Update and record activity if we processed any instructions.
1450 if (inst_num) {
1451 if (exeStatus == Idle) {
1452 exeStatus = Running;
1453 }

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1587 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1588 }
1589
1590 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1591
1592 //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1593 if (fromCommit->commitInfo[tid].uncached) {
1594 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1595 fromCommit->commitInfo[tid].uncachedLoad->setAtCommit();
1596 } else {
1597 instQueue.scheduleNonSpec(
1598 fromCommit->commitInfo[tid].nonSpecSeqNum);
1599 }
1600 }
1601
1602 if (broadcast_free_entries) {
1603 toFetch->iewInfo[tid].iqCount =

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