1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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365template<class Impl>
366void
367DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
368{
369 DPRINTF(IEW, "Setting scoreboard pointer.\n");
370 scoreboard = sb_ptr;
371}
372
373template <class Impl>
374void
375DefaultIEW<Impl>::switchOut()
376{
377 // IEW is ready to switch out at any time.
378 cpu->signalSwitched();
379}
380

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1168
1169 list<unsigned>::iterator threads = (*activeThreads).begin();
1170
1171 while (threads != (*activeThreads).end()) {
1172 unsigned tid = *threads++;
1173 fetchRedirect[tid] = false;
1174 }
1175
1176 // Uncomment this if you want to see all available instructions.
1177// printAvailableInsts();
1178
1179 // Execute/writeback any instructions that are available.
1180 int insts_to_execute = fromIssue->size;
1181 int inst_num = 0;
1182 for (; inst_num < insts_to_execute;
1183 ++inst_num) {
1184
1185 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");

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1334 // mark scoreboard that this instruction is finally complete.
1335 // Either have IEW have direct access to scoreboard, or have this
1336 // as part of backwards communication.
1337 for (int inst_num = 0; inst_num < issueWidth &&
1338 toCommit->insts[inst_num]; inst_num++) {
1339 DynInstPtr inst = toCommit->insts[inst_num];
1340 int tid = inst->threadNumber;
1341
1342 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n",
1343 inst->seqNum, inst->readPC());
1344
1345 iewInstsToCommit[tid]++;
1346
1347 // Some instructions will be sent to commit without having
1348 // executed because they need commit to handle them.
1349 // E.g. Uncached loads have not actually executed when they
1350 // are first sent to commit. Instead commit must tell the LSQ
1351 // when it's ready to execute the uncached load.

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