iew.hh (5557:03c186e416aa) iew.hh (5999:3cf8e71257e0)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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460
461 /** Maximum size of the skid buffer. */
462 unsigned skidBufferMax;
463
464 /** Is this stage switched out. */
465 bool switchedOut;
466
467 /** Stat for total number of idle cycles. */
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 451 unchanged lines hidden (view full) ---

460
461 /** Maximum size of the skid buffer. */
462 unsigned skidBufferMax;
463
464 /** Is this stage switched out. */
465 bool switchedOut;
466
467 /** Stat for total number of idle cycles. */
468 Stats::Scalar<> iewIdleCycles;
468 Stats::Scalar iewIdleCycles;
469 /** Stat for total number of squashing cycles. */
469 /** Stat for total number of squashing cycles. */
470 Stats::Scalar<> iewSquashCycles;
470 Stats::Scalar iewSquashCycles;
471 /** Stat for total number of blocking cycles. */
471 /** Stat for total number of blocking cycles. */
472 Stats::Scalar<> iewBlockCycles;
472 Stats::Scalar iewBlockCycles;
473 /** Stat for total number of unblocking cycles. */
473 /** Stat for total number of unblocking cycles. */
474 Stats::Scalar<> iewUnblockCycles;
474 Stats::Scalar iewUnblockCycles;
475 /** Stat for total number of instructions dispatched. */
475 /** Stat for total number of instructions dispatched. */
476 Stats::Scalar<> iewDispatchedInsts;
476 Stats::Scalar iewDispatchedInsts;
477 /** Stat for total number of squashed instructions dispatch skips. */
477 /** Stat for total number of squashed instructions dispatch skips. */
478 Stats::Scalar<> iewDispSquashedInsts;
478 Stats::Scalar iewDispSquashedInsts;
479 /** Stat for total number of dispatched load instructions. */
479 /** Stat for total number of dispatched load instructions. */
480 Stats::Scalar<> iewDispLoadInsts;
480 Stats::Scalar iewDispLoadInsts;
481 /** Stat for total number of dispatched store instructions. */
481 /** Stat for total number of dispatched store instructions. */
482 Stats::Scalar<> iewDispStoreInsts;
482 Stats::Scalar iewDispStoreInsts;
483 /** Stat for total number of dispatched non speculative instructions. */
483 /** Stat for total number of dispatched non speculative instructions. */
484 Stats::Scalar<> iewDispNonSpecInsts;
484 Stats::Scalar iewDispNonSpecInsts;
485 /** Stat for number of times the IQ becomes full. */
485 /** Stat for number of times the IQ becomes full. */
486 Stats::Scalar<> iewIQFullEvents;
486 Stats::Scalar iewIQFullEvents;
487 /** Stat for number of times the LSQ becomes full. */
487 /** Stat for number of times the LSQ becomes full. */
488 Stats::Scalar<> iewLSQFullEvents;
488 Stats::Scalar iewLSQFullEvents;
489 /** Stat for total number of memory ordering violation events. */
489 /** Stat for total number of memory ordering violation events. */
490 Stats::Scalar<> memOrderViolationEvents;
490 Stats::Scalar memOrderViolationEvents;
491 /** Stat for total number of incorrect predicted taken branches. */
491 /** Stat for total number of incorrect predicted taken branches. */
492 Stats::Scalar<> predictedTakenIncorrect;
492 Stats::Scalar predictedTakenIncorrect;
493 /** Stat for total number of incorrect predicted not taken branches. */
493 /** Stat for total number of incorrect predicted not taken branches. */
494 Stats::Scalar<> predictedNotTakenIncorrect;
494 Stats::Scalar predictedNotTakenIncorrect;
495 /** Stat for total number of mispredicted branches detected at execute. */
496 Stats::Formula branchMispredicts;
497
498 /** Stat for total number of executed instructions. */
495 /** Stat for total number of mispredicted branches detected at execute. */
496 Stats::Formula branchMispredicts;
497
498 /** Stat for total number of executed instructions. */
499 Stats::Scalar<> iewExecutedInsts;
499 Stats::Scalar iewExecutedInsts;
500 /** Stat for total number of executed load instructions. */
500 /** Stat for total number of executed load instructions. */
501 Stats::Vector<> iewExecLoadInsts;
501 Stats::Vector iewExecLoadInsts;
502 /** Stat for total number of executed store instructions. */
502 /** Stat for total number of executed store instructions. */
503// Stats::Scalar<> iewExecStoreInsts;
503// Stats::Scalar iewExecStoreInsts;
504 /** Stat for total number of squashed instructions skipped at execute. */
504 /** Stat for total number of squashed instructions skipped at execute. */
505 Stats::Scalar<> iewExecSquashedInsts;
505 Stats::Scalar iewExecSquashedInsts;
506 /** Number of executed software prefetches. */
506 /** Number of executed software prefetches. */
507 Stats::Vector<> iewExecutedSwp;
507 Stats::Vector iewExecutedSwp;
508 /** Number of executed nops. */
508 /** Number of executed nops. */
509 Stats::Vector<> iewExecutedNop;
509 Stats::Vector iewExecutedNop;
510 /** Number of executed meomory references. */
510 /** Number of executed meomory references. */
511 Stats::Vector<> iewExecutedRefs;
511 Stats::Vector iewExecutedRefs;
512 /** Number of executed branches. */
512 /** Number of executed branches. */
513 Stats::Vector<> iewExecutedBranches;
513 Stats::Vector iewExecutedBranches;
514 /** Number of executed store instructions. */
515 Stats::Formula iewExecStoreInsts;
516 /** Number of instructions executed per cycle. */
517 Stats::Formula iewExecRate;
518
519 /** Number of instructions sent to commit. */
514 /** Number of executed store instructions. */
515 Stats::Formula iewExecStoreInsts;
516 /** Number of instructions executed per cycle. */
517 Stats::Formula iewExecRate;
518
519 /** Number of instructions sent to commit. */
520 Stats::Vector<> iewInstsToCommit;
520 Stats::Vector iewInstsToCommit;
521 /** Number of instructions that writeback. */
521 /** Number of instructions that writeback. */
522 Stats::Vector<> writebackCount;
522 Stats::Vector writebackCount;
523 /** Number of instructions that wake consumers. */
523 /** Number of instructions that wake consumers. */
524 Stats::Vector<> producerInst;
524 Stats::Vector producerInst;
525 /** Number of instructions that wake up from producers. */
525 /** Number of instructions that wake up from producers. */
526 Stats::Vector<> consumerInst;
526 Stats::Vector consumerInst;
527 /** Number of instructions that were delayed in writing back due
528 * to resource contention.
529 */
527 /** Number of instructions that were delayed in writing back due
528 * to resource contention.
529 */
530 Stats::Vector<> wbPenalized;
530 Stats::Vector wbPenalized;
531 /** Number of instructions per cycle written back. */
532 Stats::Formula wbRate;
533 /** Average number of woken instructions per writeback. */
534 Stats::Formula wbFanout;
535 /** Number of instructions per cycle delayed in writing back . */
536 Stats::Formula wbPenalizedRate;
537};
538
539#endif // __CPU_O3_IEW_HH__
531 /** Number of instructions per cycle written back. */
532 Stats::Formula wbRate;
533 /** Average number of woken instructions per writeback. */
534 Stats::Formula wbFanout;
535 /** Number of instructions per cycle delayed in writing back . */
536 Stats::Formula wbPenalizedRate;
537};
538
539#endif // __CPU_O3_IEW_HH__