iew.hh (5215:68f719ce5496) iew.hh (5529:9ae69b9cd7fd)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 27 unchanged lines hidden (view full) ---

36#include <queue>
37
38#include "base/statistics.hh"
39#include "base/timebuf.hh"
40#include "cpu/o3/comm.hh"
41#include "cpu/o3/scoreboard.hh"
42#include "cpu/o3/lsq.hh"
43
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 27 unchanged lines hidden (view full) ---

36#include <queue>
37
38#include "base/statistics.hh"
39#include "base/timebuf.hh"
40#include "cpu/o3/comm.hh"
41#include "cpu/o3/scoreboard.hh"
42#include "cpu/o3/lsq.hh"
43
44class DerivO3CPUParams;
44class FUPool;
45
46/**
47 * DefaultIEW handles both single threaded and SMT IEW
48 * (issue/execute/writeback). It handles the dispatching of
49 * instructions to the LSQ/IQ as part of the issue stage, and has the
50 * IQ try to issue instructions each cycle. The execute latency is
51 * actually tied into the issue latency to allow the IQ to be able to

--- 13 unchanged lines hidden (view full) ---

65template<class Impl>
66class DefaultIEW
67{
68 private:
69 //Typedefs from Impl
70 typedef typename Impl::CPUPol CPUPol;
71 typedef typename Impl::DynInstPtr DynInstPtr;
72 typedef typename Impl::O3CPU O3CPU;
45class FUPool;
46
47/**
48 * DefaultIEW handles both single threaded and SMT IEW
49 * (issue/execute/writeback). It handles the dispatching of
50 * instructions to the LSQ/IQ as part of the issue stage, and has the
51 * IQ try to issue instructions each cycle. The execute latency is
52 * actually tied into the issue latency to allow the IQ to be able to

--- 13 unchanged lines hidden (view full) ---

66template<class Impl>
67class DefaultIEW
68{
69 private:
70 //Typedefs from Impl
71 typedef typename Impl::CPUPol CPUPol;
72 typedef typename Impl::DynInstPtr DynInstPtr;
73 typedef typename Impl::O3CPU O3CPU;
73 typedef typename Impl::Params Params;
74
75 typedef typename CPUPol::IQ IQ;
76 typedef typename CPUPol::RenameMap RenameMap;
77 typedef typename CPUPol::LSQ LSQ;
78
79 typedef typename CPUPol::TimeStruct TimeStruct;
80 typedef typename CPUPol::IEWStruct IEWStruct;
81 typedef typename CPUPol::RenameStruct RenameStruct;

--- 28 unchanged lines hidden (view full) ---

110 StageStatus dispatchStatus[Impl::MaxThreads];
111 /** Execute status. */
112 StageStatus exeStatus;
113 /** Writeback status. */
114 StageStatus wbStatus;
115
116 public:
117 /** Constructs a DefaultIEW with the given parameters. */
74
75 typedef typename CPUPol::IQ IQ;
76 typedef typename CPUPol::RenameMap RenameMap;
77 typedef typename CPUPol::LSQ LSQ;
78
79 typedef typename CPUPol::TimeStruct TimeStruct;
80 typedef typename CPUPol::IEWStruct IEWStruct;
81 typedef typename CPUPol::RenameStruct RenameStruct;

--- 28 unchanged lines hidden (view full) ---

110 StageStatus dispatchStatus[Impl::MaxThreads];
111 /** Execute status. */
112 StageStatus exeStatus;
113 /** Writeback status. */
114 StageStatus wbStatus;
115
116 public:
117 /** Constructs a DefaultIEW with the given parameters. */
118 DefaultIEW(O3CPU *_cpu, Params *params);
118 DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params);
119
120 /** Returns the name of the DefaultIEW stage. */
121 std::string name() const;
122
123 /** Registers statistics. */
124 void regStats();
125
126 /** Initializes stage; sends back the number of free IQ and LSQ entries. */

--- 410 unchanged lines hidden --- 		119
120 /** Returns the name of the DefaultIEW stage. */
121 std::string name() const;
122
123 /** Registers statistics. */
124 void regStats();
125
126 /** Initializes stage; sends back the number of free IQ and LSQ entries. */

--- 410 unchanged lines hidden ---