iew.hh (3125:febd811bccc6) iew.hh (4329:52057dbec096)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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110 StageStatus dispatchStatus[Impl::MaxThreads];
111 /** Execute status. */
112 StageStatus exeStatus;
113 /** Writeback status. */
114 StageStatus wbStatus;
115
116 public:
117 /** Constructs a DefaultIEW with the given parameters. */
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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110 StageStatus dispatchStatus[Impl::MaxThreads];
111 /** Execute status. */
112 StageStatus exeStatus;
113 /** Writeback status. */
114 StageStatus wbStatus;
115
116 public:
117 /** Constructs a DefaultIEW with the given parameters. */
118 DefaultIEW(Params *params);
118 DefaultIEW(O3CPU *_cpu, Params *params);
119
120 /** Returns the name of the DefaultIEW stage. */
121 std::string name() const;
122
123 /** Registers statistics. */
124 void regStats();
125
126 /** Initializes stage; sends back the number of free IQ and LSQ entries. */
127 void initStage();
128
129 /** Returns the dcache port. */
130 Port *getDcachePort() { return ldstQueue.getDcachePort(); }
131
119
120 /** Returns the name of the DefaultIEW stage. */
121 std::string name() const;
122
123 /** Registers statistics. */
124 void regStats();
125
126 /** Initializes stage; sends back the number of free IQ and LSQ entries. */
127 void initStage();
128
129 /** Returns the dcache port. */
130 Port *getDcachePort() { return ldstQueue.getDcachePort(); }
131
132 /** Sets CPU pointer for IEW, IQ, and LSQ. */
133 void setCPU(O3CPU *cpu_ptr);
134
135 /** Sets main time buffer used for backwards communication. */
136 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
137
138 /** Sets time buffer for getting instructions coming from rename. */
139 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
140
141 /** Sets time buffer to pass on instructions to commit. */
142 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);

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362 std::queue<DynInstPtr> insts[Impl::MaxThreads];
363
364 /** Skid buffer between rename and IEW. */
365 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
366
367 /** Scoreboard pointer. */
368 Scoreboard* scoreboard;
369
132 /** Sets main time buffer used for backwards communication. */
133 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
134
135 /** Sets time buffer for getting instructions coming from rename. */
136 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
137
138 /** Sets time buffer to pass on instructions to commit. */
139 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);

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359 std::queue<DynInstPtr> insts[Impl::MaxThreads];
360
361 /** Skid buffer between rename and IEW. */
362 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
363
364 /** Scoreboard pointer. */
365 Scoreboard* scoreboard;
366
370 public:
371 /** Instruction queue. */
372 IQ instQueue;
373
374 /** Load / store queue. */
375 LSQ ldstQueue;
376
377 /** Pointer to the functional unit pool. */
378 FUPool *fuPool;
379
380 private:
381 /** CPU pointer. */
382 O3CPU *cpu;
383
384 /** Records if IEW has written to the time buffer this cycle, so that the
385 * CPU can deschedule itself if there is no activity.
386 */
387 bool wroteToTimeBuffer;

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393
394 /** Stages that are telling IEW to stall. */
395 Stalls stalls[Impl::MaxThreads];
396
397 /** Debug function to print instructions that are issued this cycle. */
398 void printAvailableInsts();
399
400 public:
367 private:
368 /** CPU pointer. */
369 O3CPU *cpu;
370
371 /** Records if IEW has written to the time buffer this cycle, so that the
372 * CPU can deschedule itself if there is no activity.
373 */
374 bool wroteToTimeBuffer;

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380
381 /** Stages that are telling IEW to stall. */
382 Stalls stalls[Impl::MaxThreads];
383
384 /** Debug function to print instructions that are issued this cycle. */
385 void printAvailableInsts();
386
387 public:
388 /** Instruction queue. */
389 IQ instQueue;
390
391 /** Load / store queue. */
392 LSQ ldstQueue;
393
394 /** Pointer to the functional unit pool. */
395 FUPool *fuPool;
401 /** Records if the LSQ needs to be updated on the next cycle, so that
402 * IEW knows if there will be activity on the next cycle.
403 */
404 bool updateLSQNextCycle;
405
406 private:
407 /** Records if there is a fetch redirect on this cycle for each thread. */
408 bool fetchRedirect[Impl::MaxThreads];

--- 143 unchanged lines hidden --- 		396 /** Records if the LSQ needs to be updated on the next cycle, so that
397 * IEW knows if there will be activity on the next cycle.
398 */
399 bool updateLSQNextCycle;
400
401 private:
402 /** Records if there is a fetch redirect on this cycle for each thread. */
403 bool fetchRedirect[Impl::MaxThreads];

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