iew.hh (2935:d1223a6c9156) iew.hh (3125:febd811bccc6)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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211 /** Returns if the LSQ has any stores to writeback. */
212 bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
213
214 void incrWb(InstSeqNum &sn)
215 {
216 if (++wbOutstanding == wbMax)
217 ableToIssue = false;
218 DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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211 /** Returns if the LSQ has any stores to writeback. */
212 bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
213
214 void incrWb(InstSeqNum &sn)
215 {
216 if (++wbOutstanding == wbMax)
217 ableToIssue = false;
218 DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
219 assert(wbOutstanding <= wbMax);
219#ifdef DEBUG
220 wbList.insert(sn);
221#endif
222 }
223
224 void decrWb(InstSeqNum &sn)
225 {
226 if (wbOutstanding-- == wbMax)
227 ableToIssue = true;
228 DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
220#ifdef DEBUG
221 wbList.insert(sn);
222#endif
223 }
224
225 void decrWb(InstSeqNum &sn)
226 {
227 if (wbOutstanding-- == wbMax)
228 ableToIssue = true;
229 DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
230 assert(wbOutstanding >= 0);
229#ifdef DEBUG
230 assert(wbList.find(sn) != wbList.end());
231 wbList.erase(sn);
232#endif
233 }
234
235#ifdef DEBUG
236 std::set<InstSeqNum> wbList;

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445 /** Cycle number within the queue of instructions being written back.
446 * Used in case there are too many instructions writing back at the current
447 * cycle and writesbacks need to be scheduled for the future. See comments
448 * in instToCommit().
449 */
450 unsigned wbCycle;
451
452 /** Number of instructions in flight that will writeback. */
231#ifdef DEBUG
232 assert(wbList.find(sn) != wbList.end());
233 wbList.erase(sn);
234#endif
235 }
236
237#ifdef DEBUG
238 std::set<InstSeqNum> wbList;

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447 /** Cycle number within the queue of instructions being written back.
448 * Used in case there are too many instructions writing back at the current
449 * cycle and writesbacks need to be scheduled for the future. See comments
450 * in instToCommit().
451 */
452 unsigned wbCycle;
453
454 /** Number of instructions in flight that will writeback. */
453 unsigned wbOutstanding;
454
455
456 /** Number of instructions in flight that will writeback. */
457 int wbOutstanding;
458
455 /** Writeback width. */
456 unsigned wbWidth;
457
458 /** Writeback width * writeback depth, where writeback depth is
459 * the number of cycles of writing back instructions that can be
460 * buffered. */
461 unsigned wbMax;
462

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502 Stats::Scalar<> predictedNotTakenIncorrect;
503 /** Stat for total number of mispredicted branches detected at execute. */
504 Stats::Formula branchMispredicts;
505
506 /** Stat for total number of executed instructions. */
507 Stats::Scalar<> iewExecutedInsts;
508 /** Stat for total number of executed load instructions. */
509 Stats::Vector<> iewExecLoadInsts;
459 /** Writeback width. */
460 unsigned wbWidth;
461
462 /** Writeback width * writeback depth, where writeback depth is
463 * the number of cycles of writing back instructions that can be
464 * buffered. */
465 unsigned wbMax;
466

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506 Stats::Scalar<> predictedNotTakenIncorrect;
507 /** Stat for total number of mispredicted branches detected at execute. */
508 Stats::Formula branchMispredicts;
509
510 /** Stat for total number of executed instructions. */
511 Stats::Scalar<> iewExecutedInsts;
512 /** Stat for total number of executed load instructions. */
513 Stats::Vector<> iewExecLoadInsts;
514 /** Stat for total number of executed store instructions. */
515// Stats::Scalar<> iewExecStoreInsts;
510 /** Stat for total number of squashed instructions skipped at execute. */
511 Stats::Scalar<> iewExecSquashedInsts;
512 /** Number of executed software prefetches. */
513 Stats::Vector<> iewExecutedSwp;
514 /** Number of executed nops. */
515 Stats::Vector<> iewExecutedNop;
516 /** Number of executed meomory references. */
517 Stats::Vector<> iewExecutedRefs;

--- 28 unchanged lines hidden --- 		516 /** Stat for total number of squashed instructions skipped at execute. */
517 Stats::Scalar<> iewExecSquashedInsts;
518 /** Number of executed software prefetches. */
519 Stats::Vector<> iewExecutedSwp;
520 /** Number of executed nops. */
521 Stats::Vector<> iewExecutedNop;
522 /** Number of executed meomory references. */
523 Stats::Vector<> iewExecutedRefs;

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