iew.hh (2733:e0eac8fc5774) iew.hh (2820:7fde0b0f8f78)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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199 inline void activateStage();
200
201 /** Tells CPU that the IEW stage is inactive and idle. */
202 inline void deactivateStage();
203
204 /** Returns if the LSQ has any stores to writeback. */
205 bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
206
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 190 unchanged lines hidden (view full) ---

199 inline void activateStage();
200
201 /** Tells CPU that the IEW stage is inactive and idle. */
202 inline void deactivateStage();
203
204 /** Returns if the LSQ has any stores to writeback. */
205 bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
206
207 void incrWb(InstSeqNum &sn)
208 {
209 if (++wbOutstanding == wbMax)
210 ableToIssue = false;
211 DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
212#if DEBUG
213 wbList.insert(sn);
214#endif
215 }
216
217 void decrWb(InstSeqNum &sn)
218 {
219 if (wbOutstanding-- == wbMax)
220 ableToIssue = true;
221 DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
222#if DEBUG
223 assert(wbList.find(sn) != wbList.end());
224 wbList.erase(sn);
225#endif
226 }
227
228#if DEBUG
229 std::set<InstSeqNum> wbList;
230
231 void dumpWb()
232 {
233 std::set<InstSeqNum>::iterator wb_it = wbList.begin();
234 while (wb_it != wbList.end()) {
235 cprintf("[sn:%lli]\n",
236 (*wb_it));
237 wb_it++;
238 }
239 }
240#endif
241
242 bool canIssue() { return ableToIssue; }
243
244 bool ableToIssue;
245
207 private:
208 /** Sends commit proper information for a squash due to a branch
209 * mispredict.
210 */
211 void squashDueToBranch(DynInstPtr &inst, unsigned thread_id);
212
213 /** Sends commit proper information for a squash due to a memory order
214 * violation.

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379
380 /**
381 * Issue to execute delay, in ticks. What this actually represents is
382 * the amount of time it takes for an instruction to wake up, be
383 * scheduled, and sent to a FU for execution.
384 */
385 unsigned issueToExecuteDelay;
386
246 private:
247 /** Sends commit proper information for a squash due to a branch
248 * mispredict.
249 */
250 void squashDueToBranch(DynInstPtr &inst, unsigned thread_id);
251
252 /** Sends commit proper information for a squash due to a memory order
253 * violation.

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418
419 /**
420 * Issue to execute delay, in ticks. What this actually represents is
421 * the amount of time it takes for an instruction to wake up, be
422 * scheduled, and sent to a FU for execution.
423 */
424 unsigned issueToExecuteDelay;
425
387 /** Width of issue's read path, in instructions. The read path is both
388 * the skid buffer and the rename instruction queue.
389 * Note to self: is this really different than issueWidth?
390 */
391 unsigned issueReadWidth;
426 /** Width of dispatch, in instructions. */
427 unsigned dispatchWidth;
392
393 /** Width of issue, in instructions. */
394 unsigned issueWidth;
395
396 /** Index into queue of instructions being written back. */
397 unsigned wbNumInst;
398
399 /** Cycle number within the queue of instructions being written back.
400 * Used in case there are too many instructions writing back at the current
401 * cycle and writesbacks need to be scheduled for the future. See comments
402 * in instToCommit().
403 */
404 unsigned wbCycle;
405
428
429 /** Width of issue, in instructions. */
430 unsigned issueWidth;
431
432 /** Index into queue of instructions being written back. */
433 unsigned wbNumInst;
434
435 /** Cycle number within the queue of instructions being written back.
436 * Used in case there are too many instructions writing back at the current
437 * cycle and writesbacks need to be scheduled for the future. See comments
438 * in instToCommit().
439 */
440 unsigned wbCycle;
441
442 /** Number of instructions in flight that will writeback. */
443 unsigned wbOutstanding;
444
445 /** Writeback width. */
446 unsigned wbWidth;
447
448 /** Writeback width * writeback depth, where writeback depth is
449 * the number of cycles of writing back instructions that can be
450 * buffered. */
451 unsigned wbMax;
452
406 /** Number of active threads. */
407 unsigned numThreads;
408
409 /** Pointer to list of active threads. */
410 std::list<unsigned> *activeThreads;
411
412 /** Maximum size of the skid buffer. */
413 unsigned skidBufferMax;

--- 75 unchanged lines hidden --- 		453 /** Number of active threads. */
454 unsigned numThreads;
455
456 /** Pointer to list of active threads. */
457 std::list<unsigned> *activeThreads;
458
459 /** Maximum size of the skid buffer. */
460 unsigned skidBufferMax;

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