iew.hh (2727:91e17c7ee622) iew.hh (2733:e0eac8fc5774)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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63 */
64template<class Impl>
65class DefaultIEW
66{
67 private:
68 //Typedefs from Impl
69 typedef typename Impl::CPUPol CPUPol;
70 typedef typename Impl::DynInstPtr DynInstPtr;
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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63 */
64template<class Impl>
65class DefaultIEW
66{
67 private:
68 //Typedefs from Impl
69 typedef typename Impl::CPUPol CPUPol;
70 typedef typename Impl::DynInstPtr DynInstPtr;
71 typedef typename Impl::FullCPU FullCPU;
71 typedef typename Impl::O3CPU O3CPU;
72 typedef typename Impl::Params Params;
73
74 typedef typename CPUPol::IQ IQ;
75 typedef typename CPUPol::RenameMap RenameMap;
76 typedef typename CPUPol::LSQ LSQ;
77
78 typedef typename CPUPol::TimeStruct TimeStruct;
79 typedef typename CPUPol::IEWStruct IEWStruct;
80 typedef typename CPUPol::RenameStruct RenameStruct;
81 typedef typename CPUPol::IssueStruct IssueStruct;
82
72 typedef typename Impl::Params Params;
73
74 typedef typename CPUPol::IQ IQ;
75 typedef typename CPUPol::RenameMap RenameMap;
76 typedef typename CPUPol::LSQ LSQ;
77
78 typedef typename CPUPol::TimeStruct TimeStruct;
79 typedef typename CPUPol::IEWStruct IEWStruct;
80 typedef typename CPUPol::RenameStruct RenameStruct;
81 typedef typename CPUPol::IssueStruct IssueStruct;
82
83 friend class Impl::FullCPU;
83 friend class Impl::O3CPU;
84 friend class CPUPol::IQ;
85
86 public:
87 /** Overall IEW stage status. Used to determine if the CPU can
88 * deschedule itself due to a lack of activity.
89 */
90 enum Status {
91 Active,

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121
122 /** Registers statistics. */
123 void regStats();
124
125 /** Initializes stage; sends back the number of free IQ and LSQ entries. */
126 void initStage();
127
128 /** Sets CPU pointer for IEW, IQ, and LSQ. */
84 friend class CPUPol::IQ;
85
86 public:
87 /** Overall IEW stage status. Used to determine if the CPU can
88 * deschedule itself due to a lack of activity.
89 */
90 enum Status {
91 Active,

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121
122 /** Registers statistics. */
123 void regStats();
124
125 /** Initializes stage; sends back the number of free IQ and LSQ entries. */
126 void initStage();
127
128 /** Sets CPU pointer for IEW, IQ, and LSQ. */
129 void setCPU(FullCPU *cpu_ptr);
129 void setCPU(O3CPU *cpu_ptr);
130
131 /** Sets main time buffer used for backwards communication. */
132 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
133
134 /** Sets time buffer for getting instructions coming from rename. */
135 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
136
137 /** Sets time buffer to pass on instructions to commit. */

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326 /** Load / store queue. */
327 LSQ ldstQueue;
328
329 /** Pointer to the functional unit pool. */
330 FUPool *fuPool;
331
332 private:
333 /** CPU pointer. */
130
131 /** Sets main time buffer used for backwards communication. */
132 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
133
134 /** Sets time buffer for getting instructions coming from rename. */
135 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
136
137 /** Sets time buffer to pass on instructions to commit. */

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326 /** Load / store queue. */
327 LSQ ldstQueue;
328
329 /** Pointer to the functional unit pool. */
330 FUPool *fuPool;
331
332 private:
333 /** CPU pointer. */
334 FullCPU *cpu;
334 O3CPU *cpu;
335
336 /** Records if IEW has written to the time buffer this cycle, so that the
337 * CPU can deschedule itself if there is no activity.
338 */
339 bool wroteToTimeBuffer;
340
341 /** Source of possible stalls. */
342 struct Stalls {

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336 /** Records if IEW has written to the time buffer this cycle, so that the
337 * CPU can deschedule itself if there is no activity.
338 */
339 bool wroteToTimeBuffer;
340
341 /** Source of possible stalls. */
342 struct Stalls {

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