1/*
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2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
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2 * Copyright (c) 2004-2005 The Regents of The University of Michigan |
3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 * 28 * Authors: Kevin Lim |
29 */ 30
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29#ifndef __CPU_O3_IEW_HH__
30#define __CPU_O3_IEW_HH__
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31//Todo: Update with statuses. 32//Need to handle delaying writes to the writeback bus if it's full at the 33//given time. |
34
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35#ifndef __CPU_O3_CPU_SIMPLE_IEW_HH__ 36#define __CPU_O3_CPU_SIMPLE_IEW_HH__ 37 |
38#include <queue> 39
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40#include "config/full_system.hh" |
41#include "base/statistics.hh" 42#include "base/timebuf.hh"
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36#include "config/full_system.hh"
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43#include "cpu/o3/comm.hh"
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38#include "cpu/o3/scoreboard.hh"
39#include "cpu/o3/lsq.hh"
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44
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41class FUPool;
42
43/**
44 * DefaultIEW handles both single threaded and SMT IEW
45 * (issue/execute/writeback). It handles the dispatching of
46 * instructions to the LSQ/IQ as part of the issue stage, and has the
47 * IQ try to issue instructions each cycle. The execute latency is
48 * actually tied into the issue latency to allow the IQ to be able to
49 * do back-to-back scheduling without having to speculatively schedule
50 * instructions. This happens by having the IQ have access to the
51 * functional units, and the IQ gets the execution latencies from the
52 * FUs when it issues instructions. Instructions reach the execute
53 * stage on the last cycle of their execution, which is when the IQ
54 * knows to wake up any dependent instructions, allowing back to back
55 * scheduling. The execute portion of IEW separates memory
56 * instructions from non-memory instructions, either telling the LSQ
57 * to execute the instruction, or executing the instruction directly.
58 * The writeback portion of IEW completes the instructions by waking
59 * up any dependents, and marking the register ready on the
60 * scoreboard.
61 */
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45template<class Impl>
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63class DefaultIEW
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46class SimpleIEW |
47{ 48 private: 49 //Typedefs from Impl 50 typedef typename Impl::CPUPol CPUPol; 51 typedef typename Impl::DynInstPtr DynInstPtr; 52 typedef typename Impl::FullCPU FullCPU; 53 typedef typename Impl::Params Params; 54 55 typedef typename CPUPol::IQ IQ; 56 typedef typename CPUPol::RenameMap RenameMap;
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74 typedef typename CPUPol::LSQ LSQ;
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57 typedef typename CPUPol::LDSTQ LDSTQ; |
58 59 typedef typename CPUPol::TimeStruct TimeStruct; 60 typedef typename CPUPol::IEWStruct IEWStruct; 61 typedef typename CPUPol::RenameStruct RenameStruct; 62 typedef typename CPUPol::IssueStruct IssueStruct; 63 64 friend class Impl::FullCPU;
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82 friend class CPUPol::IQ;
83
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65 public:
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85 /** Overall IEW stage status. Used to determine if the CPU can
86 * deschedule itself due to a lack of activity.
87 */
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66 enum Status {
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89 Active,
90 Inactive
91 };
92
93 /** Status for Issue, Execute, and Writeback stages. */
94 enum StageStatus {
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67 Running, 68 Blocked, 69 Idle,
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98 StartSquash,
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70 Squashing, 71 Unblocking 72 }; 73 74 private:
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104 /** Overall stage status. */
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75 Status _status;
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106 /** Dispatch status. */
107 StageStatus dispatchStatus[Impl::MaxThreads];
108 /** Execute status. */
109 StageStatus exeStatus;
110 /** Writeback status. */
111 StageStatus wbStatus;
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76 Status _issueStatus; 77 Status _exeStatus; 78 Status _wbStatus; |
79 80 public:
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114 /** LdWriteback event for a load completion. */
115 class LdWritebackEvent : public Event {
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81 class WritebackEvent : public Event { |
82 private:
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117 /** Instruction that is writing back data to the register file. */
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83 DynInstPtr inst;
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119 /** Pointer to IEW stage. */
120 DefaultIEW<Impl> *iewStage;
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84 SimpleIEW<Impl> *iewStage; |
85 86 public:
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123 /** Constructs a load writeback event. */
124 LdWritebackEvent(DynInstPtr &_inst, DefaultIEW<Impl> *_iew);
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87 WritebackEvent(DynInstPtr &_inst, SimpleIEW<Impl> *_iew); |
88
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126 /** Processes writeback event. */
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89 virtual void process();
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128 /** Returns the description of the writeback event. */
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90 virtual const char *description(); 91 }; 92 93 public:
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133 /** Constructs a DefaultIEW with the given parameters. */
134 DefaultIEW(Params *params);
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94 SimpleIEW(Params ¶ms); |
95
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136 /** Returns the name of the DefaultIEW stage. */
137 std::string name() const;
138
139 /** Registers statistics. */
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96 void regStats(); 97
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142 /** Initializes stage; sends back the number of free IQ and LSQ entries. */
143 void initStage();
144
145 /** Sets CPU pointer for IEW, IQ, and LSQ. */
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98 void setCPU(FullCPU *cpu_ptr); 99
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148 /** Sets main time buffer used for backwards communication. */
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100 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 101
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151 /** Sets time buffer for getting instructions coming from rename. */
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102 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 103
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154 /** Sets time buffer to pass on instructions to commit. */
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104 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 105
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157 /** Sets pointer to list of active threads. */
158 void setActiveThreads(std::list<unsigned> *at_ptr);
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106 void setRenameMap(RenameMap *rm_ptr); |
107
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160 /** Sets pointer to the scoreboard. */
161 void setScoreboard(Scoreboard *sb_ptr);
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108 void squash(); |
109
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163 void switchOut();
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110 void squashDueToBranch(DynInstPtr &inst); |
111
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165 void doSwitchOut();
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112 void squashDueToMem(DynInstPtr &inst); |
113
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167 void takeOverFrom();
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114 void block(); |
115
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169 bool isSwitchedOut() { return switchedOut; }
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116 inline void unblock(); |
117
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171 /** Sets page table pointer within LSQ. */
172// void setPageTable(PageTable *pt_ptr);
173
174 /** Squashes instructions in IEW for a specific thread. */
175 void squash(unsigned tid);
176
177 /** Wakes all dependents of a completed instruction. */
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118 void wakeDependents(DynInstPtr &inst); 119
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180 /** Tells memory dependence unit that a memory instruction needs to be
181 * rescheduled. It will re-execute once replayMemInst() is called.
182 */
183 void rescheduleMemInst(DynInstPtr &inst);
184
185 /** Re-executes all rescheduled memory instructions. */
186 void replayMemInst(DynInstPtr &inst);
187
188 /** Sends an instruction to commit through the time buffer. */
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120 void instToCommit(DynInstPtr &inst); 121
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191 /** Inserts unused instructions of a thread into the skid buffer. */
192 void skidInsert(unsigned tid);
193
194 /** Returns the max of the number of entries in all of the skid buffers. */
195 int skidCount();
196
197 /** Returns if all of the skid buffers are empty. */
198 bool skidsEmpty();
199
200 /** Updates overall IEW status based on all of the stages' statuses. */
201 void updateStatus();
202
203 /** Resets entries of the IQ and the LSQ. */
204 void resetEntries();
205
206 /** Tells the CPU to wakeup if it has descheduled itself due to no
207 * activity. Used mainly by the LdWritebackEvent.
208 */
209 void wakeCPU();
210
211 /** Reports to the CPU that there is activity this cycle. */
212 void activityThisCycle();
213
214 /** Tells CPU that the IEW stage is active and running. */
215 inline void activateStage();
216
217 /** Tells CPU that the IEW stage is inactive and idle. */
218 inline void deactivateStage();
219
220 /** Returns if the LSQ has any stores to writeback. */
221 bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
222
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122 private:
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224 /** Sends commit proper information for a squash due to a branch
225 * mispredict.
226 */
227 void squashDueToBranch(DynInstPtr &inst, unsigned thread_id);
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123 void dispatchInsts(); |
124
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229 /** Sends commit proper information for a squash due to a memory order
230 * violation.
231 */
232 void squashDueToMemOrder(DynInstPtr &inst, unsigned thread_id);
233
234 /** Sends commit proper information for a squash due to memory becoming
235 * blocked (younger issued instructions must be retried).
236 */
237 void squashDueToMemBlocked(DynInstPtr &inst, unsigned thread_id);
238
239 /** Sets Dispatch to blocked, and signals back to other stages to block. */
240 void block(unsigned thread_id);
241
242 /** Unblocks Dispatch if the skid buffer is empty, and signals back to
243 * other stages to unblock.
244 */
245 void unblock(unsigned thread_id);
246
247 /** Determines proper actions to take given Dispatch's status. */
248 void dispatch(unsigned tid);
249
250 /** Dispatches instructions to IQ and LSQ. */
251 void dispatchInsts(unsigned tid);
252
253 /** Executes instructions. In the case of memory operations, it informs the
254 * LSQ to execute the instructions. Also handles any redirects that occur
255 * due to the executed instructions.
256 */
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125 void executeInsts(); 126
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259 /** Writebacks instructions. In our model, the instruction's execute()
260 * function atomically reads registers, executes, and writes registers.
261 * Thus this writeback only wakes up dependent instructions, and informs
262 * the scoreboard of registers becoming ready.
263 */
264 void writebackInsts();
265
266 /** Returns the number of valid, non-squashed instructions coming from
267 * rename to dispatch.
268 */
269 unsigned validInstsFromRename();
270
271 /** Reads the stall signals. */
272 void readStallSignals(unsigned tid);
273
274 /** Checks if any of the stall conditions are currently true. */
275 bool checkStall(unsigned tid);
276
277 /** Processes inputs and changes state accordingly. */
278 void checkSignalsAndUpdate(unsigned tid);
279
280 /** Sorts instructions coming from rename into lists separated by thread. */
281 void sortInsts();
282
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127 public:
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284 /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and
285 * Writeback to run for one cycle.
286 */
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128 void tick(); 129
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289 private:
290 void updateExeInstStats(DynInstPtr &inst);
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130 void iew(); |
131
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292 /** Pointer to main time buffer used for backwards communication. */
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132 //Interfaces to objects inside and outside of IEW. 133 /** Time buffer interface. */ |
134 TimeBuffer<TimeStruct> *timeBuffer; 135
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295 /** Wire to write information heading to previous stages. */
296 typename TimeBuffer<TimeStruct>::wire toFetch;
297
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136 /** Wire to get commit's output from backwards time buffer. */ 137 typename TimeBuffer<TimeStruct>::wire fromCommit; 138 139 /** Wire to write information heading to previous stages. */ 140 typename TimeBuffer<TimeStruct>::wire toRename; 141 142 /** Rename instruction queue interface. */ 143 TimeBuffer<RenameStruct> *renameQueue; 144 145 /** Wire to get rename's output from rename queue. */ 146 typename TimeBuffer<RenameStruct>::wire fromRename; 147 148 /** Issue stage queue. */ 149 TimeBuffer<IssueStruct> issueToExecQueue; 150 151 /** Wire to read information from the issue stage time queue. */ 152 typename TimeBuffer<IssueStruct>::wire fromIssue; 153 154 /** 155 * IEW stage time buffer. Holds ROB indices of instructions that 156 * can be marked as completed. 157 */ 158 TimeBuffer<IEWStruct> *iewQueue; 159 160 /** Wire to write infromation heading to commit. */ 161 typename TimeBuffer<IEWStruct>::wire toCommit; 162
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325 /** Queue of all instructions coming from rename this cycle. */
326 std::queue<DynInstPtr> insts[Impl::MaxThreads];
327
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163 //Will need internal queue to hold onto instructions coming from 164 //the rename stage in case of a stall. |
165 /** Skid buffer between rename and IEW. */
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329 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
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166 std::queue<RenameStruct> skidBuffer; |
167
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331 /** Scoreboard pointer. */
332 Scoreboard* scoreboard;
333
334 public:
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168 protected: |
169 /** Instruction queue. */ 170 IQ instQueue; 171
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338 /** Load / store queue. */
339 LSQ ldstQueue;
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172 LDSTQ ldstQueue; |
173
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341 /** Pointer to the functional unit pool. */
342 FUPool *fuPool;
343
344 private:
345 /** CPU pointer. */
346 FullCPU *cpu;
347
348 /** Records if IEW has written to the time buffer this cycle, so that the
349 * CPU can deschedule itself if there is no activity.
350 */
351 bool wroteToTimeBuffer;
352
353 /** Source of possible stalls. */
354 struct Stalls {
355 bool commit;
356 };
357
358 /** Stages that are telling IEW to stall. */
359 Stalls stalls[Impl::MaxThreads];
360
361 /** Debug function to print instructions that are issued this cycle. */
362 void printAvailableInsts();
363
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174#if !FULL_SYSTEM |
175 public:
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365 /** Records if the LSQ needs to be updated on the next cycle, so that
366 * IEW knows if there will be activity on the next cycle.
367 */
368 bool updateLSQNextCycle;
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176 void lsqWriteback(); 177#endif |
178 179 private:
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371 /** Records if there is a fetch redirect on this cycle for each thread. */
372 bool fetchRedirect[Impl::MaxThreads];
373
374 /** Used to track if all instructions have been dispatched this cycle.
375 * If they have not, then blocking must have occurred, and the instructions
376 * would already be added to the skid buffer.
377 * @todo: Fix this hack.
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180 /** Pointer to rename map. Might not want this stage to directly 181 * access this though... |
182 */
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379 bool dispatchedAllInsts;
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183 RenameMap *renameMap; |
184
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381 /** Records if the queues have been changed (inserted or issued insts),
382 * so that IEW knows to broadcast the updated amount of free entries.
383 */
384 bool updatedQueues;
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185 /** CPU interface. */ 186 FullCPU *cpu; |
187
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188 private: |
189 /** Commit to IEW delay, in ticks. */ 190 unsigned commitToIEWDelay; 191 192 /** Rename to IEW delay, in ticks. */ 193 unsigned renameToIEWDelay; 194 195 /** 196 * Issue to execute delay, in ticks. What this actually represents is 197 * the amount of time it takes for an instruction to wake up, be 198 * scheduled, and sent to a FU for execution. 199 */ 200 unsigned issueToExecuteDelay; 201 202 /** Width of issue's read path, in instructions. The read path is both 203 * the skid buffer and the rename instruction queue. 204 * Note to self: is this really different than issueWidth? 205 */ 206 unsigned issueReadWidth; 207 208 /** Width of issue, in instructions. */ 209 unsigned issueWidth; 210 211 /** Width of execute, in instructions. Might make more sense to break 212 * down into FP vs int. 213 */ 214 unsigned executeWidth; 215
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413 /** Index into queue of instructions being written back. */
414 unsigned wbNumInst;
415
416 /** Cycle number within the queue of instructions being written back.
417 * Used in case there are too many instructions writing back at the current
418 * cycle and writesbacks need to be scheduled for the future. See comments
419 * in instToCommit().
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216 /** Number of cycles stage has been squashing. Used so that the stage 217 * knows when it can start unblocking, which is when the previous stage 218 * has received the stall signal and clears up its outputs. |
219 */
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421 unsigned wbCycle;
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220 unsigned cyclesSquashing; |
221
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423 /** Number of active threads. */
424 unsigned numThreads;
425
426 /** Pointer to list of active threads. */
427 std::list<unsigned> *activeThreads;
428
429 /** Maximum size of the skid buffer. */
430 unsigned skidBufferMax;
431
432 bool switchedOut;
433
434 /** Stat for total number of idle cycles. */
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222 Stats::Scalar<> iewIdleCycles;
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436 /** Stat for total number of squashing cycles. */
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223 Stats::Scalar<> iewSquashCycles;
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438 /** Stat for total number of blocking cycles. */
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224 Stats::Scalar<> iewBlockCycles;
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440 /** Stat for total number of unblocking cycles. */
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225 Stats::Scalar<> iewUnblockCycles;
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442 /** Stat for total number of instructions dispatched. */
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226// Stats::Scalar<> iewWBInsts; |
227 Stats::Scalar<> iewDispatchedInsts;
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444 /** Stat for total number of squashed instructions dispatch skips. */
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228 Stats::Scalar<> iewDispSquashedInsts;
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446 /** Stat for total number of dispatched load instructions. */
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229 Stats::Scalar<> iewDispLoadInsts;
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448 /** Stat for total number of dispatched store instructions. */
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230 Stats::Scalar<> iewDispStoreInsts;
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450 /** Stat for total number of dispatched non speculative instructions. */
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231 Stats::Scalar<> iewDispNonSpecInsts;
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452 /** Stat for number of times the IQ becomes full. */
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232 Stats::Scalar<> iewIQFullEvents;
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454 /** Stat for number of times the LSQ becomes full. */
455 Stats::Scalar<> iewLSQFullEvents;
456 /** Stat for total number of executed instructions. */
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233 Stats::Scalar<> iewExecutedInsts;
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458 /** Stat for total number of executed load instructions. */
459 Stats::Vector<> iewExecLoadInsts;
460 /** Stat for total number of executed store instructions. */
461// Stats::Scalar<> iewExecStoreInsts;
462 /** Stat for total number of squashed instructions skipped at execute. */
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234 Stats::Scalar<> iewExecLoadInsts; 235 Stats::Scalar<> iewExecStoreInsts; |
236 Stats::Scalar<> iewExecSquashedInsts;
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464 /** Stat for total number of memory ordering violation events. */
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237 Stats::Scalar<> memOrderViolationEvents;
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466 /** Stat for total number of incorrect predicted taken branches. */
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238 Stats::Scalar<> predictedTakenIncorrect;
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468 /** Stat for total number of incorrect predicted not taken branches. */
469 Stats::Scalar<> predictedNotTakenIncorrect;
470 /** Stat for total number of mispredicted branches detected at execute. */
471 Stats::Formula branchMispredicts;
472
473 Stats::Vector<> exeSwp;
474 Stats::Vector<> exeNop;
475 Stats::Vector<> exeRefs;
476 Stats::Vector<> exeBranches;
477
478// Stats::Vector<> issued_ops;
479/*
480 Stats::Vector<> stat_fu_busy;
481 Stats::Vector2d<> stat_fuBusy;
482 Stats::Vector<> dist_unissued;
483 Stats::Vector2d<> stat_issued_inst_type;
484*/
485 Stats::Formula issueRate;
486 Stats::Formula iewExecStoreInsts;
487// Stats::Formula issue_op_rate;
488// Stats::Formula fu_busy_rate;
489
490 Stats::Vector<> iewInstsToCommit;
491 Stats::Vector<> writebackCount;
492 Stats::Vector<> producerInst;
493 Stats::Vector<> consumerInst;
494 Stats::Vector<> wbPenalized;
495
496 Stats::Formula wbRate;
497 Stats::Formula wbFanout;
498 Stats::Formula wbPenalizedRate;
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239}; 240
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501#endif // __CPU_O3_IEW_HH__
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241#endif // __CPU_O3_CPU_IEW_HH__ |
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