1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 247 unchanged lines hidden (view full) --- 256 void readStallSignals(unsigned tid); 257 258 /** Checks if any of the stall conditions are currently true. */ 259 bool checkStall(unsigned tid); 260 261 /** Processes inputs and changes state accordingly. */ 262 void checkSignalsAndUpdate(unsigned tid); 263 |
264 /** Removes instructions from rename from a thread's instruction list. */ 265 void emptyRenameInsts(unsigned tid); 266 |
267 /** Sorts instructions coming from rename into lists separated by thread. */ 268 void sortInsts(); 269 270 public: 271 /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and 272 * Writeback to run for one cycle. 273 */ 274 void tick(); --- 113 unchanged lines hidden (view full) --- 388 * the skid buffer and the rename instruction queue. 389 * Note to self: is this really different than issueWidth? 390 */ 391 unsigned issueReadWidth; 392 393 /** Width of issue, in instructions. */ 394 unsigned issueWidth; 395 |
396 /** Index into queue of instructions being written back. */ 397 unsigned wbNumInst; 398 399 /** Cycle number within the queue of instructions being written back. 400 * Used in case there are too many instructions writing back at the current 401 * cycle and writesbacks need to be scheduled for the future. See comments 402 * in instToCommit(). 403 */ --- 97 unchanged lines hidden --- |