1/* |
2 * Copyright (c) 2010-2012, 2014 ARM Limited |
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 165 unchanged lines hidden (view full) --- 176 /** Tells memory dependence unit that a memory instruction needs to be 177 * rescheduled. It will re-execute once replayMemInst() is called. 178 */ 179 void rescheduleMemInst(DynInstPtr &inst); 180 181 /** Re-executes all rescheduled memory instructions. */ 182 void replayMemInst(DynInstPtr &inst); 183 |
184 /** Moves memory instruction onto the list of cache blocked instructions */ 185 void blockMemInst(DynInstPtr &inst); 186 187 /** Notifies that the cache has become unblocked */ 188 void cacheUnblocked(); 189 |
190 /** Sends an instruction to commit through the time buffer. */ 191 void instToCommit(DynInstPtr &inst); 192 193 /** Inserts unused instructions of a thread into the skid buffer. */ 194 void skidInsert(ThreadID tid); 195 196 /** Returns the max of the number of entries in all of the skid buffers. */ 197 int skidCount(); --- 36 unchanged lines hidden (view full) --- 234 */ 235 void squashDueToBranch(DynInstPtr &inst, ThreadID tid); 236 237 /** Sends commit proper information for a squash due to a memory order 238 * violation. 239 */ 240 void squashDueToMemOrder(DynInstPtr &inst, ThreadID tid); 241 |
242 /** Sets Dispatch to blocked, and signals back to other stages to block. */ 243 void block(ThreadID tid); 244 245 /** Unblocks Dispatch if the skid buffer is empty, and signals back to 246 * other stages to unblock. 247 */ 248 void unblock(ThreadID tid); 249 --- 237 unchanged lines hidden --- |