1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 205 unchanged lines hidden (view full) --- 214 inline void deactivateStage(); 215 216 /** Returns if the LSQ has any stores to writeback. */ 217 bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); } 218 219 /** Returns if the LSQ has any stores to writeback. */ 220 bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); } 221 |
222 /** Check misprediction */ 223 void checkMisprediction(DynInstPtr &inst); 224 225 private: 226 /** Sends commit proper information for a squash due to a branch 227 * mispredict. 228 */ 229 void squashDueToBranch(DynInstPtr &inst, ThreadID tid); --- 174 unchanged lines hidden (view full) --- 404 405 /** Cycle number within the queue of instructions being written back. 406 * Used in case there are too many instructions writing back at the current 407 * cycle and writesbacks need to be scheduled for the future. See comments 408 * in instToCommit(). 409 */ 410 unsigned wbCycle; 411 |
412 /** Writeback width. */ 413 unsigned wbWidth; 414 |
415 /** Number of active threads. */ 416 ThreadID numThreads; 417 418 /** Pointer to list of active threads. */ 419 std::list<ThreadID> *activeThreads; 420 421 /** Maximum size of the skid buffer. */ 422 unsigned skidBufferMax; --- 74 unchanged lines hidden --- |