2c2
< * Copyright (c) 2004-2005 The Regents of The University of Michigan
---
> * Copyright (c) 2004-2006 The Regents of The University of Michigan
27,28d26
< *
< * Authors: Kevin Lim
31,33c29,30
< //Todo: Update with statuses.
< //Need to handle delaying writes to the writeback bus if it's full at the
< //given time.
---
> #ifndef __CPU_O3_IEW_HH__
> #define __CPU_O3_IEW_HH__
35,37d31
< #ifndef __CPU_O3_CPU_SIMPLE_IEW_HH__
< #define __CPU_O3_CPU_SIMPLE_IEW_HH__
<
40d33
< #include "config/full_system.hh"
42a36
> #include "config/full_system.hh"
43a38,39
> #include "cpu/o3/scoreboard.hh"
> #include "cpu/o3/lsq.hh"
44a41,61
> class FUPool;
>
> /**
> * DefaultIEW handles both single threaded and SMT IEW
> * (issue/execute/writeback). It handles the dispatching of
> * instructions to the LSQ/IQ as part of the issue stage, and has the
> * IQ try to issue instructions each cycle. The execute latency is
> * actually tied into the issue latency to allow the IQ to be able to
> * do back-to-back scheduling without having to speculatively schedule
> * instructions. This happens by having the IQ have access to the
> * functional units, and the IQ gets the execution latencies from the
> * FUs when it issues instructions. Instructions reach the execute
> * stage on the last cycle of their execution, which is when the IQ
> * knows to wake up any dependent instructions, allowing back to back
> * scheduling. The execute portion of IEW separates memory
> * instructions from non-memory instructions, either telling the LSQ
> * to execute the instruction, or executing the instruction directly.
> * The writeback portion of IEW completes the instructions by waking
> * up any dependents, and marking the register ready on the
> * scoreboard.
> */
46c63
< class SimpleIEW
---
> class DefaultIEW
57c74
< typedef typename CPUPol::LDSTQ LDSTQ;
---
> typedef typename CPUPol::LSQ LSQ;
64a82,83
> friend class CPUPol::IQ;
>
65a85,87
> /** Overall IEW stage status. Used to determine if the CPU can
> * deschedule itself due to a lack of activity.
> */
66a89,94
> Active,
> Inactive
> };
>
> /** Status for Issue, Execute, and Writeback stages. */
> enum StageStatus {
69a98
> StartSquash,
74a104
> /** Overall stage status. */
76,78c106,111
< Status _issueStatus;
< Status _exeStatus;
< Status _wbStatus;
---
> /** Dispatch status. */
> StageStatus dispatchStatus[Impl::MaxThreads];
> /** Execute status. */
> StageStatus exeStatus;
> /** Writeback status. */
> StageStatus wbStatus;
81,84c114,115
< class WritebackEvent : public Event {
< private:
< DynInstPtr inst;
< SimpleIEW<Impl> *iewStage;
---
> /** Constructs a DefaultIEW with the given parameters. */
> DefaultIEW(Params *params);
86,87c117,118
< public:
< WritebackEvent(DynInstPtr &_inst, SimpleIEW<Impl> *_iew);
---
> /** Returns the name of the DefaultIEW stage. */
> std::string name() const;
89,95c120
< virtual void process();
< virtual const char *description();
< };
<
< public:
< SimpleIEW(Params ¶ms);
<
---
> /** Registers statistics. */
97a123,126
> /** Initializes stage; sends back the number of free IQ and LSQ entries. */
> void initStage();
>
> /** Sets CPU pointer for IEW, IQ, and LSQ. */
99a129
> /** Sets main time buffer used for backwards communication. */
101a132
> /** Sets time buffer for getting instructions coming from rename. */
103a135
> /** Sets time buffer to pass on instructions to commit. */
106c138,139
< void setRenameMap(RenameMap *rm_ptr);
---
> /** Sets pointer to list of active threads. */
> void setActiveThreads(std::list<unsigned> *at_ptr);
108c141,142
< void squash();
---
> /** Sets pointer to the scoreboard. */
> void setScoreboard(Scoreboard *sb_ptr);
110c144
< void squashDueToBranch(DynInstPtr &inst);
---
> void switchOut();
112c146
< void squashDueToMem(DynInstPtr &inst);
---
> void doSwitchOut();
114c148
< void block();
---
> void takeOverFrom();
116c150
< inline void unblock();
---
> bool isSwitchedOut() { return switchedOut; }
117a152,158
> /** Sets page table pointer within LSQ. */
> // void setPageTable(PageTable *pt_ptr);
>
> /** Squashes instructions in IEW for a specific thread. */
> void squash(unsigned tid);
>
> /** Wakes all dependents of a completed instruction. */
119a161,169
> /** Tells memory dependence unit that a memory instruction needs to be
> * rescheduled. It will re-execute once replayMemInst() is called.
> */
> void rescheduleMemInst(DynInstPtr &inst);
>
> /** Re-executes all rescheduled memory instructions. */
> void replayMemInst(DynInstPtr &inst);
>
> /** Sends an instruction to commit through the time buffer. */
121a172,203
> /** Inserts unused instructions of a thread into the skid buffer. */
> void skidInsert(unsigned tid);
>
> /** Returns the max of the number of entries in all of the skid buffers. */
> int skidCount();
>
> /** Returns if all of the skid buffers are empty. */
> bool skidsEmpty();
>
> /** Updates overall IEW status based on all of the stages' statuses. */
> void updateStatus();
>
> /** Resets entries of the IQ and the LSQ. */
> void resetEntries();
>
> /** Tells the CPU to wakeup if it has descheduled itself due to no
> * activity. Used mainly by the LdWritebackEvent.
> */
> void wakeCPU();
>
> /** Reports to the CPU that there is activity this cycle. */
> void activityThisCycle();
>
> /** Tells CPU that the IEW stage is active and running. */
> inline void activateStage();
>
> /** Tells CPU that the IEW stage is inactive and idle. */
> inline void deactivateStage();
>
> /** Returns if the LSQ has any stores to writeback. */
> bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
>
123c205,208
< void dispatchInsts();
---
> /** Sends commit proper information for a squash due to a branch
> * mispredict.
> */
> void squashDueToBranch(DynInstPtr &inst, unsigned thread_id);
124a210,237
> /** Sends commit proper information for a squash due to a memory order
> * violation.
> */
> void squashDueToMemOrder(DynInstPtr &inst, unsigned thread_id);
>
> /** Sends commit proper information for a squash due to memory becoming
> * blocked (younger issued instructions must be retried).
> */
> void squashDueToMemBlocked(DynInstPtr &inst, unsigned thread_id);
>
> /** Sets Dispatch to blocked, and signals back to other stages to block. */
> void block(unsigned thread_id);
>
> /** Unblocks Dispatch if the skid buffer is empty, and signals back to
> * other stages to unblock.
> */
> void unblock(unsigned thread_id);
>
> /** Determines proper actions to take given Dispatch's status. */
> void dispatch(unsigned tid);
>
> /** Dispatches instructions to IQ and LSQ. */
> void dispatchInsts(unsigned tid);
>
> /** Executes instructions. In the case of memory operations, it informs the
> * LSQ to execute the instructions. Also handles any redirects that occur
> * due to the executed instructions.
> */
126a240,263
> /** Writebacks instructions. In our model, the instruction's execute()
> * function atomically reads registers, executes, and writes registers.
> * Thus this writeback only wakes up dependent instructions, and informs
> * the scoreboard of registers becoming ready.
> */
> void writebackInsts();
>
> /** Returns the number of valid, non-squashed instructions coming from
> * rename to dispatch.
> */
> unsigned validInstsFromRename();
>
> /** Reads the stall signals. */
> void readStallSignals(unsigned tid);
>
> /** Checks if any of the stall conditions are currently true. */
> bool checkStall(unsigned tid);
>
> /** Processes inputs and changes state accordingly. */
> void checkSignalsAndUpdate(unsigned tid);
>
> /** Sorts instructions coming from rename into lists separated by thread. */
> void sortInsts();
>
127a265,267
> /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and
> * Writeback to run for one cycle.
> */
130c270,271
< void iew();
---
> private:
> void updateExeInstStats(DynInstPtr &inst);
132,133c273
< //Interfaces to objects inside and outside of IEW.
< /** Time buffer interface. */
---
> /** Pointer to main time buffer used for backwards communication. */
135a276,278
> /** Wire to write information heading to previous stages. */
> typename TimeBuffer<TimeStruct>::wire toFetch;
>
163,164c306,308
< //Will need internal queue to hold onto instructions coming from
< //the rename stage in case of a stall.
---
> /** Queue of all instructions coming from rename this cycle. */
> std::queue<DynInstPtr> insts[Impl::MaxThreads];
>
166c310
< std::queue<RenameStruct> skidBuffer;
---
> std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
168c312,315
< protected:
---
> /** Scoreboard pointer. */
> Scoreboard* scoreboard;
>
> public:
172c319,320
< LDSTQ ldstQueue;
---
> /** Load / store queue. */
> LSQ ldstQueue;
174,177c322,323
< #if !FULL_SYSTEM
< public:
< void lsqWriteback();
< #endif
---
> /** Pointer to the functional unit pool. */
> FUPool *fuPool;
180,181c326,330
< /** Pointer to rename map. Might not want this stage to directly
< * access this though...
---
> /** CPU pointer. */
> FullCPU *cpu;
>
> /** Records if IEW has written to the time buffer this cycle, so that the
> * CPU can deschedule itself if there is no activity.
183c332
< RenameMap *renameMap;
---
> bool wroteToTimeBuffer;
185,186c334,337
< /** CPU interface. */
< FullCPU *cpu;
---
> /** Source of possible stalls. */
> struct Stalls {
> bool commit;
> };
187a339,350
> /** Stages that are telling IEW to stall. */
> Stalls stalls[Impl::MaxThreads];
>
> /** Debug function to print instructions that are issued this cycle. */
> void printAvailableInsts();
>
> public:
> /** Records if the LSQ needs to be updated on the next cycle, so that
> * IEW knows if there will be activity on the next cycle.
> */
> bool updateLSQNextCycle;
>
188a352,366
> /** Records if there is a fetch redirect on this cycle for each thread. */
> bool fetchRedirect[Impl::MaxThreads];
>
> /** Used to track if all instructions have been dispatched this cycle.
> * If they have not, then blocking must have occurred, and the instructions
> * would already be added to the skid buffer.
> * @todo: Fix this hack.
> */
> bool dispatchedAllInsts;
>
> /** Records if the queues have been changed (inserted or issued insts),
> * so that IEW knows to broadcast the updated amount of free entries.
> */
> bool updatedQueues;
>
216,218c394,400
< /** Number of cycles stage has been squashing. Used so that the stage
< * knows when it can start unblocking, which is when the previous stage
< * has received the stall signal and clears up its outputs.
---
> /** Index into queue of instructions being written back. */
> unsigned wbNumInst;
>
> /** Cycle number within the queue of instructions being written back.
> * Used in case there are too many instructions writing back at the current
> * cycle and writesbacks need to be scheduled for the future. See comments
> * in instToCommit().
220c402
< unsigned cyclesSquashing;
---
> unsigned wbCycle;
221a404,415
> /** Number of active threads. */
> unsigned numThreads;
>
> /** Pointer to list of active threads. */
> std::list<unsigned> *activeThreads;
>
> /** Maximum size of the skid buffer. */
> unsigned skidBufferMax;
>
> bool switchedOut;
>
> /** Stat for total number of idle cycles. */
222a417
> /** Stat for total number of squashing cycles. */
223a419
> /** Stat for total number of blocking cycles. */
224a421
> /** Stat for total number of unblocking cycles. */
226c423
< // Stats::Scalar<> iewWBInsts;
---
> /** Stat for total number of instructions dispatched. */
227a425
> /** Stat for total number of squashed instructions dispatch skips. */
228a427
> /** Stat for total number of dispatched load instructions. */
229a429
> /** Stat for total number of dispatched store instructions. */
230a431
> /** Stat for total number of dispatched non speculative instructions. */
231a433
> /** Stat for number of times the IQ becomes full. */
232a435,437
> /** Stat for number of times the LSQ becomes full. */
> Stats::Scalar<> iewLSQFullEvents;
> /** Stat for total number of executed instructions. */
234,235c439,443
< Stats::Scalar<> iewExecLoadInsts;
< Stats::Scalar<> iewExecStoreInsts;
---
> /** Stat for total number of executed load instructions. */
> Stats::Vector<> iewExecLoadInsts;
> /** Stat for total number of executed store instructions. */
> // Stats::Scalar<> iewExecStoreInsts;
> /** Stat for total number of squashed instructions skipped at execute. */
236a445
> /** Stat for total number of memory ordering violation events. */
237a447
> /** Stat for total number of incorrect predicted taken branches. */
238a449,479
> /** Stat for total number of incorrect predicted not taken branches. */
> Stats::Scalar<> predictedNotTakenIncorrect;
> /** Stat for total number of mispredicted branches detected at execute. */
> Stats::Formula branchMispredicts;
>
> Stats::Vector<> exeSwp;
> Stats::Vector<> exeNop;
> Stats::Vector<> exeRefs;
> Stats::Vector<> exeBranches;
>
> // Stats::Vector<> issued_ops;
> /*
> Stats::Vector<> stat_fu_busy;
> Stats::Vector2d<> stat_fuBusy;
> Stats::Vector<> dist_unissued;
> Stats::Vector2d<> stat_issued_inst_type;
> */
> Stats::Formula issueRate;
> Stats::Formula iewExecStoreInsts;
> // Stats::Formula issue_op_rate;
> // Stats::Formula fu_busy_rate;
>
> Stats::Vector<> iewInstsToCommit;
> Stats::Vector<> writebackCount;
> Stats::Vector<> producerInst;
> Stats::Vector<> consumerInst;
> Stats::Vector<> wbPenalized;
>
> Stats::Formula wbRate;
> Stats::Formula wbFanout;
> Stats::Formula wbPenalizedRate;
241c482
< #endif // __CPU_O3_CPU_IEW_HH__
---
> #endif // __CPU_O3_IEW_HH__
< * Copyright (c) 2004-2005 The Regents of The University of Michigan
---
> * Copyright (c) 2004-2006 The Regents of The University of Michigan
27,28d26
< *
< * Authors: Kevin Lim
31,33c29,30
< //Todo: Update with statuses.
< //Need to handle delaying writes to the writeback bus if it's full at the
< //given time.
---
> #ifndef __CPU_O3_IEW_HH__
> #define __CPU_O3_IEW_HH__
35,37d31
< #ifndef __CPU_O3_CPU_SIMPLE_IEW_HH__
< #define __CPU_O3_CPU_SIMPLE_IEW_HH__
<
40d33
< #include "config/full_system.hh"
42a36
> #include "config/full_system.hh"
43a38,39
> #include "cpu/o3/scoreboard.hh"
> #include "cpu/o3/lsq.hh"
44a41,61
> class FUPool;
>
> /**
> * DefaultIEW handles both single threaded and SMT IEW
> * (issue/execute/writeback). It handles the dispatching of
> * instructions to the LSQ/IQ as part of the issue stage, and has the
> * IQ try to issue instructions each cycle. The execute latency is
> * actually tied into the issue latency to allow the IQ to be able to
> * do back-to-back scheduling without having to speculatively schedule
> * instructions. This happens by having the IQ have access to the
> * functional units, and the IQ gets the execution latencies from the
> * FUs when it issues instructions. Instructions reach the execute
> * stage on the last cycle of their execution, which is when the IQ
> * knows to wake up any dependent instructions, allowing back to back
> * scheduling. The execute portion of IEW separates memory
> * instructions from non-memory instructions, either telling the LSQ
> * to execute the instruction, or executing the instruction directly.
> * The writeback portion of IEW completes the instructions by waking
> * up any dependents, and marking the register ready on the
> * scoreboard.
> */
46c63
< class SimpleIEW
---
> class DefaultIEW
57c74
< typedef typename CPUPol::LDSTQ LDSTQ;
---
> typedef typename CPUPol::LSQ LSQ;
64a82,83
> friend class CPUPol::IQ;
>
65a85,87
> /** Overall IEW stage status. Used to determine if the CPU can
> * deschedule itself due to a lack of activity.
> */
66a89,94
> Active,
> Inactive
> };
>
> /** Status for Issue, Execute, and Writeback stages. */
> enum StageStatus {
69a98
> StartSquash,
74a104
> /** Overall stage status. */
76,78c106,111
< Status _issueStatus;
< Status _exeStatus;
< Status _wbStatus;
---
> /** Dispatch status. */
> StageStatus dispatchStatus[Impl::MaxThreads];
> /** Execute status. */
> StageStatus exeStatus;
> /** Writeback status. */
> StageStatus wbStatus;
81,84c114,115
< class WritebackEvent : public Event {
< private:
< DynInstPtr inst;
< SimpleIEW<Impl> *iewStage;
---
> /** Constructs a DefaultIEW with the given parameters. */
> DefaultIEW(Params *params);
86,87c117,118
< public:
< WritebackEvent(DynInstPtr &_inst, SimpleIEW<Impl> *_iew);
---
> /** Returns the name of the DefaultIEW stage. */
> std::string name() const;
89,95c120
< virtual void process();
< virtual const char *description();
< };
<
< public:
< SimpleIEW(Params ¶ms);
<
---
> /** Registers statistics. */
97a123,126
> /** Initializes stage; sends back the number of free IQ and LSQ entries. */
> void initStage();
>
> /** Sets CPU pointer for IEW, IQ, and LSQ. */
99a129
> /** Sets main time buffer used for backwards communication. */
101a132
> /** Sets time buffer for getting instructions coming from rename. */
103a135
> /** Sets time buffer to pass on instructions to commit. */
106c138,139
< void setRenameMap(RenameMap *rm_ptr);
---
> /** Sets pointer to list of active threads. */
> void setActiveThreads(std::list<unsigned> *at_ptr);
108c141,142
< void squash();
---
> /** Sets pointer to the scoreboard. */
> void setScoreboard(Scoreboard *sb_ptr);
110c144
< void squashDueToBranch(DynInstPtr &inst);
---
> void switchOut();
112c146
< void squashDueToMem(DynInstPtr &inst);
---
> void doSwitchOut();
114c148
< void block();
---
> void takeOverFrom();
116c150
< inline void unblock();
---
> bool isSwitchedOut() { return switchedOut; }
117a152,158
> /** Sets page table pointer within LSQ. */
> // void setPageTable(PageTable *pt_ptr);
>
> /** Squashes instructions in IEW for a specific thread. */
> void squash(unsigned tid);
>
> /** Wakes all dependents of a completed instruction. */
119a161,169
> /** Tells memory dependence unit that a memory instruction needs to be
> * rescheduled. It will re-execute once replayMemInst() is called.
> */
> void rescheduleMemInst(DynInstPtr &inst);
>
> /** Re-executes all rescheduled memory instructions. */
> void replayMemInst(DynInstPtr &inst);
>
> /** Sends an instruction to commit through the time buffer. */
121a172,203
> /** Inserts unused instructions of a thread into the skid buffer. */
> void skidInsert(unsigned tid);
>
> /** Returns the max of the number of entries in all of the skid buffers. */
> int skidCount();
>
> /** Returns if all of the skid buffers are empty. */
> bool skidsEmpty();
>
> /** Updates overall IEW status based on all of the stages' statuses. */
> void updateStatus();
>
> /** Resets entries of the IQ and the LSQ. */
> void resetEntries();
>
> /** Tells the CPU to wakeup if it has descheduled itself due to no
> * activity. Used mainly by the LdWritebackEvent.
> */
> void wakeCPU();
>
> /** Reports to the CPU that there is activity this cycle. */
> void activityThisCycle();
>
> /** Tells CPU that the IEW stage is active and running. */
> inline void activateStage();
>
> /** Tells CPU that the IEW stage is inactive and idle. */
> inline void deactivateStage();
>
> /** Returns if the LSQ has any stores to writeback. */
> bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
>
123c205,208
< void dispatchInsts();
---
> /** Sends commit proper information for a squash due to a branch
> * mispredict.
> */
> void squashDueToBranch(DynInstPtr &inst, unsigned thread_id);
124a210,237
> /** Sends commit proper information for a squash due to a memory order
> * violation.
> */
> void squashDueToMemOrder(DynInstPtr &inst, unsigned thread_id);
>
> /** Sends commit proper information for a squash due to memory becoming
> * blocked (younger issued instructions must be retried).
> */
> void squashDueToMemBlocked(DynInstPtr &inst, unsigned thread_id);
>
> /** Sets Dispatch to blocked, and signals back to other stages to block. */
> void block(unsigned thread_id);
>
> /** Unblocks Dispatch if the skid buffer is empty, and signals back to
> * other stages to unblock.
> */
> void unblock(unsigned thread_id);
>
> /** Determines proper actions to take given Dispatch's status. */
> void dispatch(unsigned tid);
>
> /** Dispatches instructions to IQ and LSQ. */
> void dispatchInsts(unsigned tid);
>
> /** Executes instructions. In the case of memory operations, it informs the
> * LSQ to execute the instructions. Also handles any redirects that occur
> * due to the executed instructions.
> */
126a240,263
> /** Writebacks instructions. In our model, the instruction's execute()
> * function atomically reads registers, executes, and writes registers.
> * Thus this writeback only wakes up dependent instructions, and informs
> * the scoreboard of registers becoming ready.
> */
> void writebackInsts();
>
> /** Returns the number of valid, non-squashed instructions coming from
> * rename to dispatch.
> */
> unsigned validInstsFromRename();
>
> /** Reads the stall signals. */
> void readStallSignals(unsigned tid);
>
> /** Checks if any of the stall conditions are currently true. */
> bool checkStall(unsigned tid);
>
> /** Processes inputs and changes state accordingly. */
> void checkSignalsAndUpdate(unsigned tid);
>
> /** Sorts instructions coming from rename into lists separated by thread. */
> void sortInsts();
>
127a265,267
> /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and
> * Writeback to run for one cycle.
> */
130c270,271
< void iew();
---
> private:
> void updateExeInstStats(DynInstPtr &inst);
132,133c273
< //Interfaces to objects inside and outside of IEW.
< /** Time buffer interface. */
---
> /** Pointer to main time buffer used for backwards communication. */
135a276,278
> /** Wire to write information heading to previous stages. */
> typename TimeBuffer<TimeStruct>::wire toFetch;
>
163,164c306,308
< //Will need internal queue to hold onto instructions coming from
< //the rename stage in case of a stall.
---
> /** Queue of all instructions coming from rename this cycle. */
> std::queue<DynInstPtr> insts[Impl::MaxThreads];
>
166c310
< std::queue<RenameStruct> skidBuffer;
---
> std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
168c312,315
< protected:
---
> /** Scoreboard pointer. */
> Scoreboard* scoreboard;
>
> public:
172c319,320
< LDSTQ ldstQueue;
---
> /** Load / store queue. */
> LSQ ldstQueue;
174,177c322,323
< #if !FULL_SYSTEM
< public:
< void lsqWriteback();
< #endif
---
> /** Pointer to the functional unit pool. */
> FUPool *fuPool;
180,181c326,330
< /** Pointer to rename map. Might not want this stage to directly
< * access this though...
---
> /** CPU pointer. */
> FullCPU *cpu;
>
> /** Records if IEW has written to the time buffer this cycle, so that the
> * CPU can deschedule itself if there is no activity.
183c332
< RenameMap *renameMap;
---
> bool wroteToTimeBuffer;
185,186c334,337
< /** CPU interface. */
< FullCPU *cpu;
---
> /** Source of possible stalls. */
> struct Stalls {
> bool commit;
> };
187a339,350
> /** Stages that are telling IEW to stall. */
> Stalls stalls[Impl::MaxThreads];
>
> /** Debug function to print instructions that are issued this cycle. */
> void printAvailableInsts();
>
> public:
> /** Records if the LSQ needs to be updated on the next cycle, so that
> * IEW knows if there will be activity on the next cycle.
> */
> bool updateLSQNextCycle;
>
188a352,366
> /** Records if there is a fetch redirect on this cycle for each thread. */
> bool fetchRedirect[Impl::MaxThreads];
>
> /** Used to track if all instructions have been dispatched this cycle.
> * If they have not, then blocking must have occurred, and the instructions
> * would already be added to the skid buffer.
> * @todo: Fix this hack.
> */
> bool dispatchedAllInsts;
>
> /** Records if the queues have been changed (inserted or issued insts),
> * so that IEW knows to broadcast the updated amount of free entries.
> */
> bool updatedQueues;
>
216,218c394,400
< /** Number of cycles stage has been squashing. Used so that the stage
< * knows when it can start unblocking, which is when the previous stage
< * has received the stall signal and clears up its outputs.
---
> /** Index into queue of instructions being written back. */
> unsigned wbNumInst;
>
> /** Cycle number within the queue of instructions being written back.
> * Used in case there are too many instructions writing back at the current
> * cycle and writesbacks need to be scheduled for the future. See comments
> * in instToCommit().
220c402
< unsigned cyclesSquashing;
---
> unsigned wbCycle;
221a404,415
> /** Number of active threads. */
> unsigned numThreads;
>
> /** Pointer to list of active threads. */
> std::list<unsigned> *activeThreads;
>
> /** Maximum size of the skid buffer. */
> unsigned skidBufferMax;
>
> bool switchedOut;
>
> /** Stat for total number of idle cycles. */
222a417
> /** Stat for total number of squashing cycles. */
223a419
> /** Stat for total number of blocking cycles. */
224a421
> /** Stat for total number of unblocking cycles. */
226c423
< // Stats::Scalar<> iewWBInsts;
---
> /** Stat for total number of instructions dispatched. */
227a425
> /** Stat for total number of squashed instructions dispatch skips. */
228a427
> /** Stat for total number of dispatched load instructions. */
229a429
> /** Stat for total number of dispatched store instructions. */
230a431
> /** Stat for total number of dispatched non speculative instructions. */
231a433
> /** Stat for number of times the IQ becomes full. */
232a435,437
> /** Stat for number of times the LSQ becomes full. */
> Stats::Scalar<> iewLSQFullEvents;
> /** Stat for total number of executed instructions. */
234,235c439,443
< Stats::Scalar<> iewExecLoadInsts;
< Stats::Scalar<> iewExecStoreInsts;
---
> /** Stat for total number of executed load instructions. */
> Stats::Vector<> iewExecLoadInsts;
> /** Stat for total number of executed store instructions. */
> // Stats::Scalar<> iewExecStoreInsts;
> /** Stat for total number of squashed instructions skipped at execute. */
236a445
> /** Stat for total number of memory ordering violation events. */
237a447
> /** Stat for total number of incorrect predicted taken branches. */
238a449,479
> /** Stat for total number of incorrect predicted not taken branches. */
> Stats::Scalar<> predictedNotTakenIncorrect;
> /** Stat for total number of mispredicted branches detected at execute. */
> Stats::Formula branchMispredicts;
>
> Stats::Vector<> exeSwp;
> Stats::Vector<> exeNop;
> Stats::Vector<> exeRefs;
> Stats::Vector<> exeBranches;
>
> // Stats::Vector<> issued_ops;
> /*
> Stats::Vector<> stat_fu_busy;
> Stats::Vector2d<> stat_fuBusy;
> Stats::Vector<> dist_unissued;
> Stats::Vector2d<> stat_issued_inst_type;
> */
> Stats::Formula issueRate;
> Stats::Formula iewExecStoreInsts;
> // Stats::Formula issue_op_rate;
> // Stats::Formula fu_busy_rate;
>
> Stats::Vector<> iewInstsToCommit;
> Stats::Vector<> writebackCount;
> Stats::Vector<> producerInst;
> Stats::Vector<> consumerInst;
> Stats::Vector<> wbPenalized;
>
> Stats::Formula wbRate;
> Stats::Formula wbFanout;
> Stats::Formula wbPenalizedRate;
241c482
< #endif // __CPU_O3_CPU_IEW_HH__
---
> #endif // __CPU_O3_IEW_HH__