2c2
< * Copyright (c) 2004-2006 The Regents of The University of Michigan
---
> * Copyright (c) 2004-2005 The Regents of The University of Michigan
26a27,28
> *
> * Authors: Kevin Lim
29,30c31,33
< #ifndef __CPU_O3_IEW_HH__
< #define __CPU_O3_IEW_HH__
---
> //Todo: Update with statuses.
> //Need to handle delaying writes to the writeback bus if it's full at the
> //given time.
31a35,37
> #ifndef __CPU_O3_CPU_SIMPLE_IEW_HH__
> #define __CPU_O3_CPU_SIMPLE_IEW_HH__
>
33a40
> #include "config/full_system.hh"
36d42
< #include "config/full_system.hh"
38,39d43
< #include "cpu/o3/scoreboard.hh"
< #include "cpu/o3/lsq.hh"
41,61d44
< class FUPool;
<
< /**
< * DefaultIEW handles both single threaded and SMT IEW
< * (issue/execute/writeback). It handles the dispatching of
< * instructions to the LSQ/IQ as part of the issue stage, and has the
< * IQ try to issue instructions each cycle. The execute latency is
< * actually tied into the issue latency to allow the IQ to be able to
< * do back-to-back scheduling without having to speculatively schedule
< * instructions. This happens by having the IQ have access to the
< * functional units, and the IQ gets the execution latencies from the
< * FUs when it issues instructions. Instructions reach the execute
< * stage on the last cycle of their execution, which is when the IQ
< * knows to wake up any dependent instructions, allowing back to back
< * scheduling. The execute portion of IEW separates memory
< * instructions from non-memory instructions, either telling the LSQ
< * to execute the instruction, or executing the instruction directly.
< * The writeback portion of IEW completes the instructions by waking
< * up any dependents, and marking the register ready on the
< * scoreboard.
< */
63c46
< class DefaultIEW
---
> class SimpleIEW
74c57
< typedef typename CPUPol::LSQ LSQ;
---
> typedef typename CPUPol::LDSTQ LDSTQ;
82,83d64
< friend class CPUPol::IQ;
<
85,87d65
< /** Overall IEW stage status. Used to determine if the CPU can
< * deschedule itself due to a lack of activity.
< */
89,94d66
< Active,
< Inactive
< };
<
< /** Status for Issue, Execute, and Writeback stages. */
< enum StageStatus {
98d69
< StartSquash,
104d74
< /** Overall stage status. */
106,111c76,78
< /** Dispatch status. */
< StageStatus dispatchStatus[Impl::MaxThreads];
< /** Execute status. */
< StageStatus exeStatus;
< /** Writeback status. */
< StageStatus wbStatus;
---
> Status _issueStatus;
> Status _exeStatus;
> Status _wbStatus;
114,115c81
< /** LdWriteback event for a load completion. */
< class LdWritebackEvent : public Event {
---
> class WritebackEvent : public Event {
117d82
< /** Instruction that is writing back data to the register file. */
119,120c84
< /** Pointer to IEW stage. */
< DefaultIEW<Impl> *iewStage;
---
> SimpleIEW<Impl> *iewStage;
123,124c87
< /** Constructs a load writeback event. */
< LdWritebackEvent(DynInstPtr &_inst, DefaultIEW<Impl> *_iew);
---
> WritebackEvent(DynInstPtr &_inst, SimpleIEW<Impl> *_iew);
126d88
< /** Processes writeback event. */
128d89
< /** Returns the description of the writeback event. */
133,134c94
< /** Constructs a DefaultIEW with the given parameters. */
< DefaultIEW(Params *params);
---
> SimpleIEW(Params ¶ms);
136,139d95
< /** Returns the name of the DefaultIEW stage. */
< std::string name() const;
<
< /** Registers statistics. */
142,145d97
< /** Initializes stage; sends back the number of free IQ and LSQ entries. */
< void initStage();
<
< /** Sets CPU pointer for IEW, IQ, and LSQ. */
148d99
< /** Sets main time buffer used for backwards communication. */
151d101
< /** Sets time buffer for getting instructions coming from rename. */
154d103
< /** Sets time buffer to pass on instructions to commit. */
157,158c106
< /** Sets pointer to list of active threads. */
< void setActiveThreads(std::list<unsigned> *at_ptr);
---
> void setRenameMap(RenameMap *rm_ptr);
160,161c108
< /** Sets pointer to the scoreboard. */
< void setScoreboard(Scoreboard *sb_ptr);
---
> void squash();
163c110
< void switchOut();
---
> void squashDueToBranch(DynInstPtr &inst);
165c112
< void doSwitchOut();
---
> void squashDueToMem(DynInstPtr &inst);
167c114
< void takeOverFrom();
---
> void block();
169c116
< bool isSwitchedOut() { return switchedOut; }
---
> inline void unblock();
171,177d117
< /** Sets page table pointer within LSQ. */
< // void setPageTable(PageTable *pt_ptr);
<
< /** Squashes instructions in IEW for a specific thread. */
< void squash(unsigned tid);
<
< /** Wakes all dependents of a completed instruction. */
180,188d119
< /** Tells memory dependence unit that a memory instruction needs to be
< * rescheduled. It will re-execute once replayMemInst() is called.
< */
< void rescheduleMemInst(DynInstPtr &inst);
<
< /** Re-executes all rescheduled memory instructions. */
< void replayMemInst(DynInstPtr &inst);
<
< /** Sends an instruction to commit through the time buffer. */
191,222d121
< /** Inserts unused instructions of a thread into the skid buffer. */
< void skidInsert(unsigned tid);
<
< /** Returns the max of the number of entries in all of the skid buffers. */
< int skidCount();
<
< /** Returns if all of the skid buffers are empty. */
< bool skidsEmpty();
<
< /** Updates overall IEW status based on all of the stages' statuses. */
< void updateStatus();
<
< /** Resets entries of the IQ and the LSQ. */
< void resetEntries();
<
< /** Tells the CPU to wakeup if it has descheduled itself due to no
< * activity. Used mainly by the LdWritebackEvent.
< */
< void wakeCPU();
<
< /** Reports to the CPU that there is activity this cycle. */
< void activityThisCycle();
<
< /** Tells CPU that the IEW stage is active and running. */
< inline void activateStage();
<
< /** Tells CPU that the IEW stage is inactive and idle. */
< inline void deactivateStage();
<
< /** Returns if the LSQ has any stores to writeback. */
< bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
<
224,227c123
< /** Sends commit proper information for a squash due to a branch
< * mispredict.
< */
< void squashDueToBranch(DynInstPtr &inst, unsigned thread_id);
---
> void dispatchInsts();
229,256d124
< /** Sends commit proper information for a squash due to a memory order
< * violation.
< */
< void squashDueToMemOrder(DynInstPtr &inst, unsigned thread_id);
<
< /** Sends commit proper information for a squash due to memory becoming
< * blocked (younger issued instructions must be retried).
< */
< void squashDueToMemBlocked(DynInstPtr &inst, unsigned thread_id);
<
< /** Sets Dispatch to blocked, and signals back to other stages to block. */
< void block(unsigned thread_id);
<
< /** Unblocks Dispatch if the skid buffer is empty, and signals back to
< * other stages to unblock.
< */
< void unblock(unsigned thread_id);
<
< /** Determines proper actions to take given Dispatch's status. */
< void dispatch(unsigned tid);
<
< /** Dispatches instructions to IQ and LSQ. */
< void dispatchInsts(unsigned tid);
<
< /** Executes instructions. In the case of memory operations, it informs the
< * LSQ to execute the instructions. Also handles any redirects that occur
< * due to the executed instructions.
< */
259,282d126
< /** Writebacks instructions. In our model, the instruction's execute()
< * function atomically reads registers, executes, and writes registers.
< * Thus this writeback only wakes up dependent instructions, and informs
< * the scoreboard of registers becoming ready.
< */
< void writebackInsts();
<
< /** Returns the number of valid, non-squashed instructions coming from
< * rename to dispatch.
< */
< unsigned validInstsFromRename();
<
< /** Reads the stall signals. */
< void readStallSignals(unsigned tid);
<
< /** Checks if any of the stall conditions are currently true. */
< bool checkStall(unsigned tid);
<
< /** Processes inputs and changes state accordingly. */
< void checkSignalsAndUpdate(unsigned tid);
<
< /** Sorts instructions coming from rename into lists separated by thread. */
< void sortInsts();
<
284,286d127
< /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and
< * Writeback to run for one cycle.
< */
289,290c130
< private:
< void updateExeInstStats(DynInstPtr &inst);
---
> void iew();
292c132,133
< /** Pointer to main time buffer used for backwards communication. */
---
> //Interfaces to objects inside and outside of IEW.
> /** Time buffer interface. */
295,297d135
< /** Wire to write information heading to previous stages. */
< typename TimeBuffer<TimeStruct>::wire toFetch;
<
325,327c163,164
< /** Queue of all instructions coming from rename this cycle. */
< std::queue<DynInstPtr> insts[Impl::MaxThreads];
<
---
> //Will need internal queue to hold onto instructions coming from
> //the rename stage in case of a stall.
329c166
< std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
---
> std::queue<RenameStruct> skidBuffer;
331,334c168
< /** Scoreboard pointer. */
< Scoreboard* scoreboard;
<
< public:
---
> protected:
338,339c172
< /** Load / store queue. */
< LSQ ldstQueue;
---
> LDSTQ ldstQueue;
341,363c174
< /** Pointer to the functional unit pool. */
< FUPool *fuPool;
<
< private:
< /** CPU pointer. */
< FullCPU *cpu;
<
< /** Records if IEW has written to the time buffer this cycle, so that the
< * CPU can deschedule itself if there is no activity.
< */
< bool wroteToTimeBuffer;
<
< /** Source of possible stalls. */
< struct Stalls {
< bool commit;
< };
<
< /** Stages that are telling IEW to stall. */
< Stalls stalls[Impl::MaxThreads];
<
< /** Debug function to print instructions that are issued this cycle. */
< void printAvailableInsts();
<
---
> #if !FULL_SYSTEM
365,368c176,177
< /** Records if the LSQ needs to be updated on the next cycle, so that
< * IEW knows if there will be activity on the next cycle.
< */
< bool updateLSQNextCycle;
---
> void lsqWriteback();
> #endif
371,377c180,181
< /** Records if there is a fetch redirect on this cycle for each thread. */
< bool fetchRedirect[Impl::MaxThreads];
<
< /** Used to track if all instructions have been dispatched this cycle.
< * If they have not, then blocking must have occurred, and the instructions
< * would already be added to the skid buffer.
< * @todo: Fix this hack.
---
> /** Pointer to rename map. Might not want this stage to directly
> * access this though...
379c183
< bool dispatchedAllInsts;
---
> RenameMap *renameMap;
381,384c185,186
< /** Records if the queues have been changed (inserted or issued insts),
< * so that IEW knows to broadcast the updated amount of free entries.
< */
< bool updatedQueues;
---
> /** CPU interface. */
> FullCPU *cpu;
385a188
> private:
413,419c216,218
< /** Index into queue of instructions being written back. */
< unsigned wbNumInst;
<
< /** Cycle number within the queue of instructions being written back.
< * Used in case there are too many instructions writing back at the current
< * cycle and writesbacks need to be scheduled for the future. See comments
< * in instToCommit().
---
> /** Number of cycles stage has been squashing. Used so that the stage
> * knows when it can start unblocking, which is when the previous stage
> * has received the stall signal and clears up its outputs.
421c220
< unsigned wbCycle;
---
> unsigned cyclesSquashing;
423,434d221
< /** Number of active threads. */
< unsigned numThreads;
<
< /** Pointer to list of active threads. */
< std::list<unsigned> *activeThreads;
<
< /** Maximum size of the skid buffer. */
< unsigned skidBufferMax;
<
< bool switchedOut;
<
< /** Stat for total number of idle cycles. */
436d222
< /** Stat for total number of squashing cycles. */
438d223
< /** Stat for total number of blocking cycles. */
440d224
< /** Stat for total number of unblocking cycles. */
442c226
< /** Stat for total number of instructions dispatched. */
---
> // Stats::Scalar<> iewWBInsts;
444d227
< /** Stat for total number of squashed instructions dispatch skips. */
446d228
< /** Stat for total number of dispatched load instructions. */
448d229
< /** Stat for total number of dispatched store instructions. */
450d230
< /** Stat for total number of dispatched non speculative instructions. */
452d231
< /** Stat for number of times the IQ becomes full. */
454,456d232
< /** Stat for number of times the LSQ becomes full. */
< Stats::Scalar<> iewLSQFullEvents;
< /** Stat for total number of executed instructions. */
458,462c234,235
< /** Stat for total number of executed load instructions. */
< Stats::Vector<> iewExecLoadInsts;
< /** Stat for total number of executed store instructions. */
< // Stats::Scalar<> iewExecStoreInsts;
< /** Stat for total number of squashed instructions skipped at execute. */
---
> Stats::Scalar<> iewExecLoadInsts;
> Stats::Scalar<> iewExecStoreInsts;
464d236
< /** Stat for total number of memory ordering violation events. */
466d237
< /** Stat for total number of incorrect predicted taken branches. */
468,498d238
< /** Stat for total number of incorrect predicted not taken branches. */
< Stats::Scalar<> predictedNotTakenIncorrect;
< /** Stat for total number of mispredicted branches detected at execute. */
< Stats::Formula branchMispredicts;
<
< Stats::Vector<> exeSwp;
< Stats::Vector<> exeNop;
< Stats::Vector<> exeRefs;
< Stats::Vector<> exeBranches;
<
< // Stats::Vector<> issued_ops;
< /*
< Stats::Vector<> stat_fu_busy;
< Stats::Vector2d<> stat_fuBusy;
< Stats::Vector<> dist_unissued;
< Stats::Vector2d<> stat_issued_inst_type;
< */
< Stats::Formula issueRate;
< Stats::Formula iewExecStoreInsts;
< // Stats::Formula issue_op_rate;
< // Stats::Formula fu_busy_rate;
<
< Stats::Vector<> iewInstsToCommit;
< Stats::Vector<> writebackCount;
< Stats::Vector<> producerInst;
< Stats::Vector<> consumerInst;
< Stats::Vector<> wbPenalized;
<
< Stats::Formula wbRate;
< Stats::Formula wbFanout;
< Stats::Formula wbPenalizedRate;
501c241
< #endif // __CPU_O3_IEW_HH__
---
> #endif // __CPU_O3_CPU_IEW_HH__
< * Copyright (c) 2004-2006 The Regents of The University of Michigan
---
> * Copyright (c) 2004-2005 The Regents of The University of Michigan
26a27,28
> *
> * Authors: Kevin Lim
29,30c31,33
< #ifndef __CPU_O3_IEW_HH__
< #define __CPU_O3_IEW_HH__
---
> //Todo: Update with statuses.
> //Need to handle delaying writes to the writeback bus if it's full at the
> //given time.
31a35,37
> #ifndef __CPU_O3_CPU_SIMPLE_IEW_HH__
> #define __CPU_O3_CPU_SIMPLE_IEW_HH__
>
33a40
> #include "config/full_system.hh"
36d42
< #include "config/full_system.hh"
38,39d43
< #include "cpu/o3/scoreboard.hh"
< #include "cpu/o3/lsq.hh"
41,61d44
< class FUPool;
<
< /**
< * DefaultIEW handles both single threaded and SMT IEW
< * (issue/execute/writeback). It handles the dispatching of
< * instructions to the LSQ/IQ as part of the issue stage, and has the
< * IQ try to issue instructions each cycle. The execute latency is
< * actually tied into the issue latency to allow the IQ to be able to
< * do back-to-back scheduling without having to speculatively schedule
< * instructions. This happens by having the IQ have access to the
< * functional units, and the IQ gets the execution latencies from the
< * FUs when it issues instructions. Instructions reach the execute
< * stage on the last cycle of their execution, which is when the IQ
< * knows to wake up any dependent instructions, allowing back to back
< * scheduling. The execute portion of IEW separates memory
< * instructions from non-memory instructions, either telling the LSQ
< * to execute the instruction, or executing the instruction directly.
< * The writeback portion of IEW completes the instructions by waking
< * up any dependents, and marking the register ready on the
< * scoreboard.
< */
63c46
< class DefaultIEW
---
> class SimpleIEW
74c57
< typedef typename CPUPol::LSQ LSQ;
---
> typedef typename CPUPol::LDSTQ LDSTQ;
82,83d64
< friend class CPUPol::IQ;
<
85,87d65
< /** Overall IEW stage status. Used to determine if the CPU can
< * deschedule itself due to a lack of activity.
< */
89,94d66
< Active,
< Inactive
< };
<
< /** Status for Issue, Execute, and Writeback stages. */
< enum StageStatus {
98d69
< StartSquash,
104d74
< /** Overall stage status. */
106,111c76,78
< /** Dispatch status. */
< StageStatus dispatchStatus[Impl::MaxThreads];
< /** Execute status. */
< StageStatus exeStatus;
< /** Writeback status. */
< StageStatus wbStatus;
---
> Status _issueStatus;
> Status _exeStatus;
> Status _wbStatus;
114,115c81
< /** LdWriteback event for a load completion. */
< class LdWritebackEvent : public Event {
---
> class WritebackEvent : public Event {
117d82
< /** Instruction that is writing back data to the register file. */
119,120c84
< /** Pointer to IEW stage. */
< DefaultIEW<Impl> *iewStage;
---
> SimpleIEW<Impl> *iewStage;
123,124c87
< /** Constructs a load writeback event. */
< LdWritebackEvent(DynInstPtr &_inst, DefaultIEW<Impl> *_iew);
---
> WritebackEvent(DynInstPtr &_inst, SimpleIEW<Impl> *_iew);
126d88
< /** Processes writeback event. */
128d89
< /** Returns the description of the writeback event. */
133,134c94
< /** Constructs a DefaultIEW with the given parameters. */
< DefaultIEW(Params *params);
---
> SimpleIEW(Params ¶ms);
136,139d95
< /** Returns the name of the DefaultIEW stage. */
< std::string name() const;
<
< /** Registers statistics. */
142,145d97
< /** Initializes stage; sends back the number of free IQ and LSQ entries. */
< void initStage();
<
< /** Sets CPU pointer for IEW, IQ, and LSQ. */
148d99
< /** Sets main time buffer used for backwards communication. */
151d101
< /** Sets time buffer for getting instructions coming from rename. */
154d103
< /** Sets time buffer to pass on instructions to commit. */
157,158c106
< /** Sets pointer to list of active threads. */
< void setActiveThreads(std::list<unsigned> *at_ptr);
---
> void setRenameMap(RenameMap *rm_ptr);
160,161c108
< /** Sets pointer to the scoreboard. */
< void setScoreboard(Scoreboard *sb_ptr);
---
> void squash();
163c110
< void switchOut();
---
> void squashDueToBranch(DynInstPtr &inst);
165c112
< void doSwitchOut();
---
> void squashDueToMem(DynInstPtr &inst);
167c114
< void takeOverFrom();
---
> void block();
169c116
< bool isSwitchedOut() { return switchedOut; }
---
> inline void unblock();
171,177d117
< /** Sets page table pointer within LSQ. */
< // void setPageTable(PageTable *pt_ptr);
<
< /** Squashes instructions in IEW for a specific thread. */
< void squash(unsigned tid);
<
< /** Wakes all dependents of a completed instruction. */
180,188d119
< /** Tells memory dependence unit that a memory instruction needs to be
< * rescheduled. It will re-execute once replayMemInst() is called.
< */
< void rescheduleMemInst(DynInstPtr &inst);
<
< /** Re-executes all rescheduled memory instructions. */
< void replayMemInst(DynInstPtr &inst);
<
< /** Sends an instruction to commit through the time buffer. */
191,222d121
< /** Inserts unused instructions of a thread into the skid buffer. */
< void skidInsert(unsigned tid);
<
< /** Returns the max of the number of entries in all of the skid buffers. */
< int skidCount();
<
< /** Returns if all of the skid buffers are empty. */
< bool skidsEmpty();
<
< /** Updates overall IEW status based on all of the stages' statuses. */
< void updateStatus();
<
< /** Resets entries of the IQ and the LSQ. */
< void resetEntries();
<
< /** Tells the CPU to wakeup if it has descheduled itself due to no
< * activity. Used mainly by the LdWritebackEvent.
< */
< void wakeCPU();
<
< /** Reports to the CPU that there is activity this cycle. */
< void activityThisCycle();
<
< /** Tells CPU that the IEW stage is active and running. */
< inline void activateStage();
<
< /** Tells CPU that the IEW stage is inactive and idle. */
< inline void deactivateStage();
<
< /** Returns if the LSQ has any stores to writeback. */
< bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
<
224,227c123
< /** Sends commit proper information for a squash due to a branch
< * mispredict.
< */
< void squashDueToBranch(DynInstPtr &inst, unsigned thread_id);
---
> void dispatchInsts();
229,256d124
< /** Sends commit proper information for a squash due to a memory order
< * violation.
< */
< void squashDueToMemOrder(DynInstPtr &inst, unsigned thread_id);
<
< /** Sends commit proper information for a squash due to memory becoming
< * blocked (younger issued instructions must be retried).
< */
< void squashDueToMemBlocked(DynInstPtr &inst, unsigned thread_id);
<
< /** Sets Dispatch to blocked, and signals back to other stages to block. */
< void block(unsigned thread_id);
<
< /** Unblocks Dispatch if the skid buffer is empty, and signals back to
< * other stages to unblock.
< */
< void unblock(unsigned thread_id);
<
< /** Determines proper actions to take given Dispatch's status. */
< void dispatch(unsigned tid);
<
< /** Dispatches instructions to IQ and LSQ. */
< void dispatchInsts(unsigned tid);
<
< /** Executes instructions. In the case of memory operations, it informs the
< * LSQ to execute the instructions. Also handles any redirects that occur
< * due to the executed instructions.
< */
259,282d126
< /** Writebacks instructions. In our model, the instruction's execute()
< * function atomically reads registers, executes, and writes registers.
< * Thus this writeback only wakes up dependent instructions, and informs
< * the scoreboard of registers becoming ready.
< */
< void writebackInsts();
<
< /** Returns the number of valid, non-squashed instructions coming from
< * rename to dispatch.
< */
< unsigned validInstsFromRename();
<
< /** Reads the stall signals. */
< void readStallSignals(unsigned tid);
<
< /** Checks if any of the stall conditions are currently true. */
< bool checkStall(unsigned tid);
<
< /** Processes inputs and changes state accordingly. */
< void checkSignalsAndUpdate(unsigned tid);
<
< /** Sorts instructions coming from rename into lists separated by thread. */
< void sortInsts();
<
284,286d127
< /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and
< * Writeback to run for one cycle.
< */
289,290c130
< private:
< void updateExeInstStats(DynInstPtr &inst);
---
> void iew();
292c132,133
< /** Pointer to main time buffer used for backwards communication. */
---
> //Interfaces to objects inside and outside of IEW.
> /** Time buffer interface. */
295,297d135
< /** Wire to write information heading to previous stages. */
< typename TimeBuffer<TimeStruct>::wire toFetch;
<
325,327c163,164
< /** Queue of all instructions coming from rename this cycle. */
< std::queue<DynInstPtr> insts[Impl::MaxThreads];
<
---
> //Will need internal queue to hold onto instructions coming from
> //the rename stage in case of a stall.
329c166
< std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
---
> std::queue<RenameStruct> skidBuffer;
331,334c168
< /** Scoreboard pointer. */
< Scoreboard* scoreboard;
<
< public:
---
> protected:
338,339c172
< /** Load / store queue. */
< LSQ ldstQueue;
---
> LDSTQ ldstQueue;
341,363c174
< /** Pointer to the functional unit pool. */
< FUPool *fuPool;
<
< private:
< /** CPU pointer. */
< FullCPU *cpu;
<
< /** Records if IEW has written to the time buffer this cycle, so that the
< * CPU can deschedule itself if there is no activity.
< */
< bool wroteToTimeBuffer;
<
< /** Source of possible stalls. */
< struct Stalls {
< bool commit;
< };
<
< /** Stages that are telling IEW to stall. */
< Stalls stalls[Impl::MaxThreads];
<
< /** Debug function to print instructions that are issued this cycle. */
< void printAvailableInsts();
<
---
> #if !FULL_SYSTEM
365,368c176,177
< /** Records if the LSQ needs to be updated on the next cycle, so that
< * IEW knows if there will be activity on the next cycle.
< */
< bool updateLSQNextCycle;
---
> void lsqWriteback();
> #endif
371,377c180,181
< /** Records if there is a fetch redirect on this cycle for each thread. */
< bool fetchRedirect[Impl::MaxThreads];
<
< /** Used to track if all instructions have been dispatched this cycle.
< * If they have not, then blocking must have occurred, and the instructions
< * would already be added to the skid buffer.
< * @todo: Fix this hack.
---
> /** Pointer to rename map. Might not want this stage to directly
> * access this though...
379c183
< bool dispatchedAllInsts;
---
> RenameMap *renameMap;
381,384c185,186
< /** Records if the queues have been changed (inserted or issued insts),
< * so that IEW knows to broadcast the updated amount of free entries.
< */
< bool updatedQueues;
---
> /** CPU interface. */
> FullCPU *cpu;
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> private:
413,419c216,218
< /** Index into queue of instructions being written back. */
< unsigned wbNumInst;
<
< /** Cycle number within the queue of instructions being written back.
< * Used in case there are too many instructions writing back at the current
< * cycle and writesbacks need to be scheduled for the future. See comments
< * in instToCommit().
---
> /** Number of cycles stage has been squashing. Used so that the stage
> * knows when it can start unblocking, which is when the previous stage
> * has received the stall signal and clears up its outputs.
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< unsigned wbCycle;
---
> unsigned cyclesSquashing;
423,434d221
< /** Number of active threads. */
< unsigned numThreads;
<
< /** Pointer to list of active threads. */
< std::list<unsigned> *activeThreads;
<
< /** Maximum size of the skid buffer. */
< unsigned skidBufferMax;
<
< bool switchedOut;
<
< /** Stat for total number of idle cycles. */
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< /** Stat for total number of squashing cycles. */
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< /** Stat for total number of blocking cycles. */
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< /** Stat for total number of unblocking cycles. */
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< /** Stat for total number of instructions dispatched. */
---
> // Stats::Scalar<> iewWBInsts;
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< /** Stat for total number of squashed instructions dispatch skips. */
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< /** Stat for total number of dispatched load instructions. */
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< /** Stat for total number of dispatched store instructions. */
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< /** Stat for total number of dispatched non speculative instructions. */
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< /** Stat for number of times the IQ becomes full. */
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< /** Stat for number of times the LSQ becomes full. */
< Stats::Scalar<> iewLSQFullEvents;
< /** Stat for total number of executed instructions. */
458,462c234,235
< /** Stat for total number of executed load instructions. */
< Stats::Vector<> iewExecLoadInsts;
< /** Stat for total number of executed store instructions. */
< // Stats::Scalar<> iewExecStoreInsts;
< /** Stat for total number of squashed instructions skipped at execute. */
---
> Stats::Scalar<> iewExecLoadInsts;
> Stats::Scalar<> iewExecStoreInsts;
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< /** Stat for total number of memory ordering violation events. */
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< /** Stat for total number of incorrect predicted taken branches. */
468,498d238
< /** Stat for total number of incorrect predicted not taken branches. */
< Stats::Scalar<> predictedNotTakenIncorrect;
< /** Stat for total number of mispredicted branches detected at execute. */
< Stats::Formula branchMispredicts;
<
< Stats::Vector<> exeSwp;
< Stats::Vector<> exeNop;
< Stats::Vector<> exeRefs;
< Stats::Vector<> exeBranches;
<
< // Stats::Vector<> issued_ops;
< /*
< Stats::Vector<> stat_fu_busy;
< Stats::Vector2d<> stat_fuBusy;
< Stats::Vector<> dist_unissued;
< Stats::Vector2d<> stat_issued_inst_type;
< */
< Stats::Formula issueRate;
< Stats::Formula iewExecStoreInsts;
< // Stats::Formula issue_op_rate;
< // Stats::Formula fu_busy_rate;
<
< Stats::Vector<> iewInstsToCommit;
< Stats::Vector<> writebackCount;
< Stats::Vector<> producerInst;
< Stats::Vector<> consumerInst;
< Stats::Vector<> wbPenalized;
<
< Stats::Formula wbRate;
< Stats::Formula wbFanout;
< Stats::Formula wbPenalizedRate;
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< #endif // __CPU_O3_IEW_HH__
---
> #endif // __CPU_O3_CPU_IEW_HH__