1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_O3_IEW_HH__
44#define __CPU_O3_IEW_HH__
45
46#include <queue>
47#include <set>
48
49#include "base/statistics.hh"
50#include "config/full_system.hh"
51#include "cpu/o3/comm.hh"
52#include "cpu/o3/lsq.hh"
53#include "cpu/o3/scoreboard.hh"
54#include "cpu/timebuf.hh"
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_O3_IEW_HH__
44#define __CPU_O3_IEW_HH__
45
46#include <queue>
47#include <set>
48
49#include "base/statistics.hh"
50#include "config/full_system.hh"
51#include "cpu/o3/comm.hh"
52#include "cpu/o3/lsq.hh"
53#include "cpu/o3/scoreboard.hh"
54#include "cpu/timebuf.hh"
|
55
56class DerivO3CPUParams;
57class FUPool;
58
59/**
60 * DefaultIEW handles both single threaded and SMT IEW
61 * (issue/execute/writeback). It handles the dispatching of
62 * instructions to the LSQ/IQ as part of the issue stage, and has the
63 * IQ try to issue instructions each cycle. The execute latency is
64 * actually tied into the issue latency to allow the IQ to be able to
65 * do back-to-back scheduling without having to speculatively schedule
66 * instructions. This happens by having the IQ have access to the
67 * functional units, and the IQ gets the execution latencies from the
68 * FUs when it issues instructions. Instructions reach the execute
69 * stage on the last cycle of their execution, which is when the IQ
70 * knows to wake up any dependent instructions, allowing back to back
71 * scheduling. The execute portion of IEW separates memory
72 * instructions from non-memory instructions, either telling the LSQ
73 * to execute the instruction, or executing the instruction directly.
74 * The writeback portion of IEW completes the instructions by waking
75 * up any dependents, and marking the register ready on the
76 * scoreboard.
77 */
78template<class Impl>
79class DefaultIEW
80{
81 private:
82 //Typedefs from Impl
83 typedef typename Impl::CPUPol CPUPol;
84 typedef typename Impl::DynInstPtr DynInstPtr;
85 typedef typename Impl::O3CPU O3CPU;
86
87 typedef typename CPUPol::IQ IQ;
88 typedef typename CPUPol::RenameMap RenameMap;
89 typedef typename CPUPol::LSQ LSQ;
90
91 typedef typename CPUPol::TimeStruct TimeStruct;
92 typedef typename CPUPol::IEWStruct IEWStruct;
93 typedef typename CPUPol::RenameStruct RenameStruct;
94 typedef typename CPUPol::IssueStruct IssueStruct;
95
96 friend class Impl::O3CPU;
97 friend class CPUPol::IQ;
98
99 public:
100 /** Overall IEW stage status. Used to determine if the CPU can
101 * deschedule itself due to a lack of activity.
102 */
103 enum Status {
104 Active,
105 Inactive
106 };
107
108 /** Status for Issue, Execute, and Writeback stages. */
109 enum StageStatus {
110 Running,
111 Blocked,
112 Idle,
113 StartSquash,
114 Squashing,
115 Unblocking
116 };
117
118 private:
119 /** Overall stage status. */
120 Status _status;
121 /** Dispatch status. */
122 StageStatus dispatchStatus[Impl::MaxThreads];
123 /** Execute status. */
124 StageStatus exeStatus;
125 /** Writeback status. */
126 StageStatus wbStatus;
127
128 public:
129 /** Constructs a DefaultIEW with the given parameters. */
130 DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params);
131
132 /** Returns the name of the DefaultIEW stage. */
133 std::string name() const;
134
135 /** Registers statistics. */
136 void regStats();
137
138 /** Initializes stage; sends back the number of free IQ and LSQ entries. */
139 void initStage();
140
141 /** Returns the dcache port. */
142 Port *getDcachePort() { return ldstQueue.getDcachePort(); }
143
144 /** Sets main time buffer used for backwards communication. */
145 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
146
147 /** Sets time buffer for getting instructions coming from rename. */
148 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
149
150 /** Sets time buffer to pass on instructions to commit. */
151 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
152
153 /** Sets pointer to list of active threads. */
154 void setActiveThreads(std::list<ThreadID> *at_ptr);
155
156 /** Sets pointer to the scoreboard. */
157 void setScoreboard(Scoreboard *sb_ptr);
158
159 /** Drains IEW stage. */
160 bool drain();
161
162 /** Resumes execution after a drain. */
163 void resume();
164
165 /** Completes switch out of IEW stage. */
166 void switchOut();
167
168 /** Takes over from another CPU's thread. */
169 void takeOverFrom();
170
171 /** Returns if IEW is switched out. */
172 bool isSwitchedOut() { return switchedOut; }
173
174 /** Squashes instructions in IEW for a specific thread. */
175 void squash(ThreadID tid);
176
177 /** Wakes all dependents of a completed instruction. */
178 void wakeDependents(DynInstPtr &inst);
179
180 /** Tells memory dependence unit that a memory instruction needs to be
181 * rescheduled. It will re-execute once replayMemInst() is called.
182 */
183 void rescheduleMemInst(DynInstPtr &inst);
184
185 /** Re-executes all rescheduled memory instructions. */
186 void replayMemInst(DynInstPtr &inst);
187
188 /** Sends an instruction to commit through the time buffer. */
189 void instToCommit(DynInstPtr &inst);
190
191 /** Inserts unused instructions of a thread into the skid buffer. */
192 void skidInsert(ThreadID tid);
193
194 /** Returns the max of the number of entries in all of the skid buffers. */
195 int skidCount();
196
197 /** Returns if all of the skid buffers are empty. */
198 bool skidsEmpty();
199
200 /** Updates overall IEW status based on all of the stages' statuses. */
201 void updateStatus();
202
203 /** Resets entries of the IQ and the LSQ. */
204 void resetEntries();
205
206 /** Tells the CPU to wakeup if it has descheduled itself due to no
207 * activity. Used mainly by the LdWritebackEvent.
208 */
209 void wakeCPU();
210
211 /** Reports to the CPU that there is activity this cycle. */
212 void activityThisCycle();
213
214 /** Tells CPU that the IEW stage is active and running. */
215 inline void activateStage();
216
217 /** Tells CPU that the IEW stage is inactive and idle. */
218 inline void deactivateStage();
219
220 /** Returns if the LSQ has any stores to writeback. */
221 bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
222
223 /** Returns if the LSQ has any stores to writeback. */
224 bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); }
225
226 void incrWb(InstSeqNum &sn)
227 {
228 if (++wbOutstanding == wbMax)
229 ableToIssue = false;
230 DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
231 assert(wbOutstanding <= wbMax);
232#ifdef DEBUG
233 wbList.insert(sn);
234#endif
235 }
236
237 void decrWb(InstSeqNum &sn)
238 {
239 if (wbOutstanding-- == wbMax)
240 ableToIssue = true;
241 DPRINTF(IEW, "wbOutstanding: %i [sn:%lli]\n", wbOutstanding, sn);
242 assert(wbOutstanding >= 0);
243#ifdef DEBUG
244 assert(wbList.find(sn) != wbList.end());
245 wbList.erase(sn);
246#endif
247 }
248
249#ifdef DEBUG
250 std::set<InstSeqNum> wbList;
251
252 void dumpWb()
253 {
254 std::set<InstSeqNum>::iterator wb_it = wbList.begin();
255 while (wb_it != wbList.end()) {
256 cprintf("[sn:%lli]\n",
257 (*wb_it));
258 wb_it++;
259 }
260 }
261#endif
262
263 bool canIssue() { return ableToIssue; }
264
265 bool ableToIssue;
266
267 /** Check misprediction */
268 void checkMisprediction(DynInstPtr &inst);
269
270 private:
271 /** Sends commit proper information for a squash due to a branch
272 * mispredict.
273 */
274 void squashDueToBranch(DynInstPtr &inst, ThreadID tid);
275
276 /** Sends commit proper information for a squash due to a memory order
277 * violation.
278 */
279 void squashDueToMemOrder(DynInstPtr &inst, ThreadID tid);
280
281 /** Sends commit proper information for a squash due to memory becoming
282 * blocked (younger issued instructions must be retried).
283 */
284 void squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid);
285
286 /** Sets Dispatch to blocked, and signals back to other stages to block. */
287 void block(ThreadID tid);
288
289 /** Unblocks Dispatch if the skid buffer is empty, and signals back to
290 * other stages to unblock.
291 */
292 void unblock(ThreadID tid);
293
294 /** Determines proper actions to take given Dispatch's status. */
295 void dispatch(ThreadID tid);
296
297 /** Dispatches instructions to IQ and LSQ. */
298 void dispatchInsts(ThreadID tid);
299
300 /** Executes instructions. In the case of memory operations, it informs the
301 * LSQ to execute the instructions. Also handles any redirects that occur
302 * due to the executed instructions.
303 */
304 void executeInsts();
305
306 /** Writebacks instructions. In our model, the instruction's execute()
307 * function atomically reads registers, executes, and writes registers.
308 * Thus this writeback only wakes up dependent instructions, and informs
309 * the scoreboard of registers becoming ready.
310 */
311 void writebackInsts();
312
313 /** Returns the number of valid, non-squashed instructions coming from
314 * rename to dispatch.
315 */
316 unsigned validInstsFromRename();
317
318 /** Reads the stall signals. */
319 void readStallSignals(ThreadID tid);
320
321 /** Checks if any of the stall conditions are currently true. */
322 bool checkStall(ThreadID tid);
323
324 /** Processes inputs and changes state accordingly. */
325 void checkSignalsAndUpdate(ThreadID tid);
326
327 /** Removes instructions from rename from a thread's instruction list. */
328 void emptyRenameInsts(ThreadID tid);
329
330 /** Sorts instructions coming from rename into lists separated by thread. */
331 void sortInsts();
332
333 public:
334 /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and
335 * Writeback to run for one cycle.
336 */
337 void tick();
338
339 private:
340 /** Updates execution stats based on the instruction. */
341 void updateExeInstStats(DynInstPtr &inst);
342
343 /** Pointer to main time buffer used for backwards communication. */
344 TimeBuffer<TimeStruct> *timeBuffer;
345
346 /** Wire to write information heading to previous stages. */
347 typename TimeBuffer<TimeStruct>::wire toFetch;
348
349 /** Wire to get commit's output from backwards time buffer. */
350 typename TimeBuffer<TimeStruct>::wire fromCommit;
351
352 /** Wire to write information heading to previous stages. */
353 typename TimeBuffer<TimeStruct>::wire toRename;
354
355 /** Rename instruction queue interface. */
356 TimeBuffer<RenameStruct> *renameQueue;
357
358 /** Wire to get rename's output from rename queue. */
359 typename TimeBuffer<RenameStruct>::wire fromRename;
360
361 /** Issue stage queue. */
362 TimeBuffer<IssueStruct> issueToExecQueue;
363
364 /** Wire to read information from the issue stage time queue. */
365 typename TimeBuffer<IssueStruct>::wire fromIssue;
366
367 /**
368 * IEW stage time buffer. Holds ROB indices of instructions that
369 * can be marked as completed.
370 */
371 TimeBuffer<IEWStruct> *iewQueue;
372
373 /** Wire to write infromation heading to commit. */
374 typename TimeBuffer<IEWStruct>::wire toCommit;
375
376 /** Queue of all instructions coming from rename this cycle. */
377 std::queue<DynInstPtr> insts[Impl::MaxThreads];
378
379 /** Skid buffer between rename and IEW. */
380 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
381
382 /** Scoreboard pointer. */
383 Scoreboard* scoreboard;
384
385 private:
386 /** CPU pointer. */
387 O3CPU *cpu;
388
389 /** Records if IEW has written to the time buffer this cycle, so that the
390 * CPU can deschedule itself if there is no activity.
391 */
392 bool wroteToTimeBuffer;
393
394 /** Source of possible stalls. */
395 struct Stalls {
396 bool commit;
397 };
398
399 /** Stages that are telling IEW to stall. */
400 Stalls stalls[Impl::MaxThreads];
401
402 /** Debug function to print instructions that are issued this cycle. */
403 void printAvailableInsts();
404
405 public:
406 /** Instruction queue. */
407 IQ instQueue;
408
409 /** Load / store queue. */
410 LSQ ldstQueue;
411
412 /** Pointer to the functional unit pool. */
413 FUPool *fuPool;
414 /** Records if the LSQ needs to be updated on the next cycle, so that
415 * IEW knows if there will be activity on the next cycle.
416 */
417 bool updateLSQNextCycle;
418
419 private:
420 /** Records if there is a fetch redirect on this cycle for each thread. */
421 bool fetchRedirect[Impl::MaxThreads];
422
423 /** Records if the queues have been changed (inserted or issued insts),
424 * so that IEW knows to broadcast the updated amount of free entries.
425 */
426 bool updatedQueues;
427
428 /** Commit to IEW delay, in ticks. */
429 unsigned commitToIEWDelay;
430
431 /** Rename to IEW delay, in ticks. */
432 unsigned renameToIEWDelay;
433
434 /**
435 * Issue to execute delay, in ticks. What this actually represents is
436 * the amount of time it takes for an instruction to wake up, be
437 * scheduled, and sent to a FU for execution.
438 */
439 unsigned issueToExecuteDelay;
440
441 /** Width of dispatch, in instructions. */
442 unsigned dispatchWidth;
443
444 /** Width of issue, in instructions. */
445 unsigned issueWidth;
446
447 /** Index into queue of instructions being written back. */
448 unsigned wbNumInst;
449
450 /** Cycle number within the queue of instructions being written back.
451 * Used in case there are too many instructions writing back at the current
452 * cycle and writesbacks need to be scheduled for the future. See comments
453 * in instToCommit().
454 */
455 unsigned wbCycle;
456
457 /** Number of instructions in flight that will writeback. */
458
459 /** Number of instructions in flight that will writeback. */
460 int wbOutstanding;
461
462 /** Writeback width. */
463 unsigned wbWidth;
464
465 /** Writeback width * writeback depth, where writeback depth is
466 * the number of cycles of writing back instructions that can be
467 * buffered. */
468 unsigned wbMax;
469
470 /** Number of active threads. */
471 ThreadID numThreads;
472
473 /** Pointer to list of active threads. */
474 std::list<ThreadID> *activeThreads;
475
476 /** Maximum size of the skid buffer. */
477 unsigned skidBufferMax;
478
479 /** Is this stage switched out. */
480 bool switchedOut;
481
482 /** Stat for total number of idle cycles. */
483 Stats::Scalar iewIdleCycles;
484 /** Stat for total number of squashing cycles. */
485 Stats::Scalar iewSquashCycles;
486 /** Stat for total number of blocking cycles. */
487 Stats::Scalar iewBlockCycles;
488 /** Stat for total number of unblocking cycles. */
489 Stats::Scalar iewUnblockCycles;
490 /** Stat for total number of instructions dispatched. */
491 Stats::Scalar iewDispatchedInsts;
492 /** Stat for total number of squashed instructions dispatch skips. */
493 Stats::Scalar iewDispSquashedInsts;
494 /** Stat for total number of dispatched load instructions. */
495 Stats::Scalar iewDispLoadInsts;
496 /** Stat for total number of dispatched store instructions. */
497 Stats::Scalar iewDispStoreInsts;
498 /** Stat for total number of dispatched non speculative instructions. */
499 Stats::Scalar iewDispNonSpecInsts;
500 /** Stat for number of times the IQ becomes full. */
501 Stats::Scalar iewIQFullEvents;
502 /** Stat for number of times the LSQ becomes full. */
503 Stats::Scalar iewLSQFullEvents;
504 /** Stat for total number of memory ordering violation events. */
505 Stats::Scalar memOrderViolationEvents;
506 /** Stat for total number of incorrect predicted taken branches. */
507 Stats::Scalar predictedTakenIncorrect;
508 /** Stat for total number of incorrect predicted not taken branches. */
509 Stats::Scalar predictedNotTakenIncorrect;
510 /** Stat for total number of mispredicted branches detected at execute. */
511 Stats::Formula branchMispredicts;
512
513 /** Stat for total number of executed instructions. */
514 Stats::Scalar iewExecutedInsts;
515 /** Stat for total number of executed load instructions. */
516 Stats::Vector iewExecLoadInsts;
517 /** Stat for total number of executed store instructions. */
518// Stats::Scalar iewExecStoreInsts;
519 /** Stat for total number of squashed instructions skipped at execute. */
520 Stats::Scalar iewExecSquashedInsts;
521 /** Number of executed software prefetches. */
522 Stats::Vector iewExecutedSwp;
523 /** Number of executed nops. */
524 Stats::Vector iewExecutedNop;
525 /** Number of executed meomory references. */
526 Stats::Vector iewExecutedRefs;
527 /** Number of executed branches. */
528 Stats::Vector iewExecutedBranches;
529 /** Number of executed store instructions. */
530 Stats::Formula iewExecStoreInsts;
531 /** Number of instructions executed per cycle. */
532 Stats::Formula iewExecRate;
533
534 /** Number of instructions sent to commit. */
535 Stats::Vector iewInstsToCommit;
536 /** Number of instructions that writeback. */
537 Stats::Vector writebackCount;
538 /** Number of instructions that wake consumers. */
539 Stats::Vector producerInst;
540 /** Number of instructions that wake up from producers. */
541 Stats::Vector consumerInst;
542 /** Number of instructions that were delayed in writing back due
543 * to resource contention.
544 */
545 Stats::Vector wbPenalized;
546 /** Number of instructions per cycle written back. */
547 Stats::Formula wbRate;
548 /** Average number of woken instructions per writeback. */
549 Stats::Formula wbFanout;
550 /** Number of instructions per cycle delayed in writing back . */
551 Stats::Formula wbPenalizedRate;
552};
553
554#endif // __CPU_O3_IEW_HH__
| 56
57class DerivO3CPUParams;
58class FUPool;
59
60/**
61 * DefaultIEW handles both single threaded and SMT IEW
62 * (issue/execute/writeback). It handles the dispatching of
63 * instructions to the LSQ/IQ as part of the issue stage, and has the
64 * IQ try to issue instructions each cycle. The execute latency is
65 * actually tied into the issue latency to allow the IQ to be able to
66 * do back-to-back scheduling without having to speculatively schedule
67 * instructions. This happens by having the IQ have access to the
68 * functional units, and the IQ gets the execution latencies from the
69 * FUs when it issues instructions. Instructions reach the execute
70 * stage on the last cycle of their execution, which is when the IQ
71 * knows to wake up any dependent instructions, allowing back to back
72 * scheduling. The execute portion of IEW separates memory
73 * instructions from non-memory instructions, either telling the LSQ
74 * to execute the instruction, or executing the instruction directly.
75 * The writeback portion of IEW completes the instructions by waking
76 * up any dependents, and marking the register ready on the
77 * scoreboard.
78 */
79template<class Impl>
80class DefaultIEW
81{
82 private:
83 //Typedefs from Impl
84 typedef typename Impl::CPUPol CPUPol;
85 typedef typename Impl::DynInstPtr DynInstPtr;
86 typedef typename Impl::O3CPU O3CPU;
87
88 typedef typename CPUPol::IQ IQ;
89 typedef typename CPUPol::RenameMap RenameMap;
90 typedef typename CPUPol::LSQ LSQ;
91
92 typedef typename CPUPol::TimeStruct TimeStruct;
93 typedef typename CPUPol::IEWStruct IEWStruct;
94 typedef typename CPUPol::RenameStruct RenameStruct;
95 typedef typename CPUPol::IssueStruct IssueStruct;
96
97 friend class Impl::O3CPU;
98 friend class CPUPol::IQ;
99
100 public:
101 /** Overall IEW stage status. Used to determine if the CPU can
102 * deschedule itself due to a lack of activity.
103 */
104 enum Status {
105 Active,
106 Inactive
107 };
108
109 /** Status for Issue, Execute, and Writeback stages. */
110 enum StageStatus {
111 Running,
112 Blocked,
113 Idle,
114 StartSquash,
115 Squashing,
116 Unblocking
117 };
118
119 private:
120 /** Overall stage status. */
121 Status _status;
122 /** Dispatch status. */
123 StageStatus dispatchStatus[Impl::MaxThreads];
124 /** Execute status. */
125 StageStatus exeStatus;
126 /** Writeback status. */
127 StageStatus wbStatus;
128
129 public:
130 /** Constructs a DefaultIEW with the given parameters. */
131 DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params);
132
133 /** Returns the name of the DefaultIEW stage. */
134 std::string name() const;
135
136 /** Registers statistics. */
137 void regStats();
138
139 /** Initializes stage; sends back the number of free IQ and LSQ entries. */
140 void initStage();
141
142 /** Returns the dcache port. */
143 Port *getDcachePort() { return ldstQueue.getDcachePort(); }
144
145 /** Sets main time buffer used for backwards communication. */
146 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
147
148 /** Sets time buffer for getting instructions coming from rename. */
149 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
150
151 /** Sets time buffer to pass on instructions to commit. */
152 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
153
154 /** Sets pointer to list of active threads. */
155 void setActiveThreads(std::list<ThreadID> *at_ptr);
156
157 /** Sets pointer to the scoreboard. */
158 void setScoreboard(Scoreboard *sb_ptr);
159
160 /** Drains IEW stage. */
161 bool drain();
162
163 /** Resumes execution after a drain. */
164 void resume();
165
166 /** Completes switch out of IEW stage. */
167 void switchOut();
168
169 /** Takes over from another CPU's thread. */
170 void takeOverFrom();
171
172 /** Returns if IEW is switched out. */
173 bool isSwitchedOut() { return switchedOut; }
174
175 /** Squashes instructions in IEW for a specific thread. */
176 void squash(ThreadID tid);
177
178 /** Wakes all dependents of a completed instruction. */
179 void wakeDependents(DynInstPtr &inst);
180
181 /** Tells memory dependence unit that a memory instruction needs to be
182 * rescheduled. It will re-execute once replayMemInst() is called.
183 */
184 void rescheduleMemInst(DynInstPtr &inst);
185
186 /** Re-executes all rescheduled memory instructions. */
187 void replayMemInst(DynInstPtr &inst);
188
189 /** Sends an instruction to commit through the time buffer. */
190 void instToCommit(DynInstPtr &inst);
191
192 /** Inserts unused instructions of a thread into the skid buffer. */
193 void skidInsert(ThreadID tid);
194
195 /** Returns the max of the number of entries in all of the skid buffers. */
196 int skidCount();
197
198 /** Returns if all of the skid buffers are empty. */
199 bool skidsEmpty();
200
201 /** Updates overall IEW status based on all of the stages' statuses. */
202 void updateStatus();
203
204 /** Resets entries of the IQ and the LSQ. */
205 void resetEntries();
206
207 /** Tells the CPU to wakeup if it has descheduled itself due to no
208 * activity. Used mainly by the LdWritebackEvent.
209 */
210 void wakeCPU();
211
212 /** Reports to the CPU that there is activity this cycle. */
213 void activityThisCycle();
214
215 /** Tells CPU that the IEW stage is active and running. */
216 inline void activateStage();
217
218 /** Tells CPU that the IEW stage is inactive and idle. */
219 inline void deactivateStage();
220
221 /** Returns if the LSQ has any stores to writeback. */
222 bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
223
224 /** Returns if the LSQ has any stores to writeback. */
225 bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); }
226
227 void incrWb(InstSeqNum &sn)
228 {
229 if (++wbOutstanding == wbMax)
230 ableToIssue = false;
231 DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
232 assert(wbOutstanding <= wbMax);
233#ifdef DEBUG
234 wbList.insert(sn);
235#endif
236 }
237
238 void decrWb(InstSeqNum &sn)
239 {
240 if (wbOutstanding-- == wbMax)
241 ableToIssue = true;
242 DPRINTF(IEW, "wbOutstanding: %i [sn:%lli]\n", wbOutstanding, sn);
243 assert(wbOutstanding >= 0);
244#ifdef DEBUG
245 assert(wbList.find(sn) != wbList.end());
246 wbList.erase(sn);
247#endif
248 }
249
250#ifdef DEBUG
251 std::set<InstSeqNum> wbList;
252
253 void dumpWb()
254 {
255 std::set<InstSeqNum>::iterator wb_it = wbList.begin();
256 while (wb_it != wbList.end()) {
257 cprintf("[sn:%lli]\n",
258 (*wb_it));
259 wb_it++;
260 }
261 }
262#endif
263
264 bool canIssue() { return ableToIssue; }
265
266 bool ableToIssue;
267
268 /** Check misprediction */
269 void checkMisprediction(DynInstPtr &inst);
270
271 private:
272 /** Sends commit proper information for a squash due to a branch
273 * mispredict.
274 */
275 void squashDueToBranch(DynInstPtr &inst, ThreadID tid);
276
277 /** Sends commit proper information for a squash due to a memory order
278 * violation.
279 */
280 void squashDueToMemOrder(DynInstPtr &inst, ThreadID tid);
281
282 /** Sends commit proper information for a squash due to memory becoming
283 * blocked (younger issued instructions must be retried).
284 */
285 void squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid);
286
287 /** Sets Dispatch to blocked, and signals back to other stages to block. */
288 void block(ThreadID tid);
289
290 /** Unblocks Dispatch if the skid buffer is empty, and signals back to
291 * other stages to unblock.
292 */
293 void unblock(ThreadID tid);
294
295 /** Determines proper actions to take given Dispatch's status. */
296 void dispatch(ThreadID tid);
297
298 /** Dispatches instructions to IQ and LSQ. */
299 void dispatchInsts(ThreadID tid);
300
301 /** Executes instructions. In the case of memory operations, it informs the
302 * LSQ to execute the instructions. Also handles any redirects that occur
303 * due to the executed instructions.
304 */
305 void executeInsts();
306
307 /** Writebacks instructions. In our model, the instruction's execute()
308 * function atomically reads registers, executes, and writes registers.
309 * Thus this writeback only wakes up dependent instructions, and informs
310 * the scoreboard of registers becoming ready.
311 */
312 void writebackInsts();
313
314 /** Returns the number of valid, non-squashed instructions coming from
315 * rename to dispatch.
316 */
317 unsigned validInstsFromRename();
318
319 /** Reads the stall signals. */
320 void readStallSignals(ThreadID tid);
321
322 /** Checks if any of the stall conditions are currently true. */
323 bool checkStall(ThreadID tid);
324
325 /** Processes inputs and changes state accordingly. */
326 void checkSignalsAndUpdate(ThreadID tid);
327
328 /** Removes instructions from rename from a thread's instruction list. */
329 void emptyRenameInsts(ThreadID tid);
330
331 /** Sorts instructions coming from rename into lists separated by thread. */
332 void sortInsts();
333
334 public:
335 /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and
336 * Writeback to run for one cycle.
337 */
338 void tick();
339
340 private:
341 /** Updates execution stats based on the instruction. */
342 void updateExeInstStats(DynInstPtr &inst);
343
344 /** Pointer to main time buffer used for backwards communication. */
345 TimeBuffer<TimeStruct> *timeBuffer;
346
347 /** Wire to write information heading to previous stages. */
348 typename TimeBuffer<TimeStruct>::wire toFetch;
349
350 /** Wire to get commit's output from backwards time buffer. */
351 typename TimeBuffer<TimeStruct>::wire fromCommit;
352
353 /** Wire to write information heading to previous stages. */
354 typename TimeBuffer<TimeStruct>::wire toRename;
355
356 /** Rename instruction queue interface. */
357 TimeBuffer<RenameStruct> *renameQueue;
358
359 /** Wire to get rename's output from rename queue. */
360 typename TimeBuffer<RenameStruct>::wire fromRename;
361
362 /** Issue stage queue. */
363 TimeBuffer<IssueStruct> issueToExecQueue;
364
365 /** Wire to read information from the issue stage time queue. */
366 typename TimeBuffer<IssueStruct>::wire fromIssue;
367
368 /**
369 * IEW stage time buffer. Holds ROB indices of instructions that
370 * can be marked as completed.
371 */
372 TimeBuffer<IEWStruct> *iewQueue;
373
374 /** Wire to write infromation heading to commit. */
375 typename TimeBuffer<IEWStruct>::wire toCommit;
376
377 /** Queue of all instructions coming from rename this cycle. */
378 std::queue<DynInstPtr> insts[Impl::MaxThreads];
379
380 /** Skid buffer between rename and IEW. */
381 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
382
383 /** Scoreboard pointer. */
384 Scoreboard* scoreboard;
385
386 private:
387 /** CPU pointer. */
388 O3CPU *cpu;
389
390 /** Records if IEW has written to the time buffer this cycle, so that the
391 * CPU can deschedule itself if there is no activity.
392 */
393 bool wroteToTimeBuffer;
394
395 /** Source of possible stalls. */
396 struct Stalls {
397 bool commit;
398 };
399
400 /** Stages that are telling IEW to stall. */
401 Stalls stalls[Impl::MaxThreads];
402
403 /** Debug function to print instructions that are issued this cycle. */
404 void printAvailableInsts();
405
406 public:
407 /** Instruction queue. */
408 IQ instQueue;
409
410 /** Load / store queue. */
411 LSQ ldstQueue;
412
413 /** Pointer to the functional unit pool. */
414 FUPool *fuPool;
415 /** Records if the LSQ needs to be updated on the next cycle, so that
416 * IEW knows if there will be activity on the next cycle.
417 */
418 bool updateLSQNextCycle;
419
420 private:
421 /** Records if there is a fetch redirect on this cycle for each thread. */
422 bool fetchRedirect[Impl::MaxThreads];
423
424 /** Records if the queues have been changed (inserted or issued insts),
425 * so that IEW knows to broadcast the updated amount of free entries.
426 */
427 bool updatedQueues;
428
429 /** Commit to IEW delay, in ticks. */
430 unsigned commitToIEWDelay;
431
432 /** Rename to IEW delay, in ticks. */
433 unsigned renameToIEWDelay;
434
435 /**
436 * Issue to execute delay, in ticks. What this actually represents is
437 * the amount of time it takes for an instruction to wake up, be
438 * scheduled, and sent to a FU for execution.
439 */
440 unsigned issueToExecuteDelay;
441
442 /** Width of dispatch, in instructions. */
443 unsigned dispatchWidth;
444
445 /** Width of issue, in instructions. */
446 unsigned issueWidth;
447
448 /** Index into queue of instructions being written back. */
449 unsigned wbNumInst;
450
451 /** Cycle number within the queue of instructions being written back.
452 * Used in case there are too many instructions writing back at the current
453 * cycle and writesbacks need to be scheduled for the future. See comments
454 * in instToCommit().
455 */
456 unsigned wbCycle;
457
458 /** Number of instructions in flight that will writeback. */
459
460 /** Number of instructions in flight that will writeback. */
461 int wbOutstanding;
462
463 /** Writeback width. */
464 unsigned wbWidth;
465
466 /** Writeback width * writeback depth, where writeback depth is
467 * the number of cycles of writing back instructions that can be
468 * buffered. */
469 unsigned wbMax;
470
471 /** Number of active threads. */
472 ThreadID numThreads;
473
474 /** Pointer to list of active threads. */
475 std::list<ThreadID> *activeThreads;
476
477 /** Maximum size of the skid buffer. */
478 unsigned skidBufferMax;
479
480 /** Is this stage switched out. */
481 bool switchedOut;
482
483 /** Stat for total number of idle cycles. */
484 Stats::Scalar iewIdleCycles;
485 /** Stat for total number of squashing cycles. */
486 Stats::Scalar iewSquashCycles;
487 /** Stat for total number of blocking cycles. */
488 Stats::Scalar iewBlockCycles;
489 /** Stat for total number of unblocking cycles. */
490 Stats::Scalar iewUnblockCycles;
491 /** Stat for total number of instructions dispatched. */
492 Stats::Scalar iewDispatchedInsts;
493 /** Stat for total number of squashed instructions dispatch skips. */
494 Stats::Scalar iewDispSquashedInsts;
495 /** Stat for total number of dispatched load instructions. */
496 Stats::Scalar iewDispLoadInsts;
497 /** Stat for total number of dispatched store instructions. */
498 Stats::Scalar iewDispStoreInsts;
499 /** Stat for total number of dispatched non speculative instructions. */
500 Stats::Scalar iewDispNonSpecInsts;
501 /** Stat for number of times the IQ becomes full. */
502 Stats::Scalar iewIQFullEvents;
503 /** Stat for number of times the LSQ becomes full. */
504 Stats::Scalar iewLSQFullEvents;
505 /** Stat for total number of memory ordering violation events. */
506 Stats::Scalar memOrderViolationEvents;
507 /** Stat for total number of incorrect predicted taken branches. */
508 Stats::Scalar predictedTakenIncorrect;
509 /** Stat for total number of incorrect predicted not taken branches. */
510 Stats::Scalar predictedNotTakenIncorrect;
511 /** Stat for total number of mispredicted branches detected at execute. */
512 Stats::Formula branchMispredicts;
513
514 /** Stat for total number of executed instructions. */
515 Stats::Scalar iewExecutedInsts;
516 /** Stat for total number of executed load instructions. */
517 Stats::Vector iewExecLoadInsts;
518 /** Stat for total number of executed store instructions. */
519// Stats::Scalar iewExecStoreInsts;
520 /** Stat for total number of squashed instructions skipped at execute. */
521 Stats::Scalar iewExecSquashedInsts;
522 /** Number of executed software prefetches. */
523 Stats::Vector iewExecutedSwp;
524 /** Number of executed nops. */
525 Stats::Vector iewExecutedNop;
526 /** Number of executed meomory references. */
527 Stats::Vector iewExecutedRefs;
528 /** Number of executed branches. */
529 Stats::Vector iewExecutedBranches;
530 /** Number of executed store instructions. */
531 Stats::Formula iewExecStoreInsts;
532 /** Number of instructions executed per cycle. */
533 Stats::Formula iewExecRate;
534
535 /** Number of instructions sent to commit. */
536 Stats::Vector iewInstsToCommit;
537 /** Number of instructions that writeback. */
538 Stats::Vector writebackCount;
539 /** Number of instructions that wake consumers. */
540 Stats::Vector producerInst;
541 /** Number of instructions that wake up from producers. */
542 Stats::Vector consumerInst;
543 /** Number of instructions that were delayed in writing back due
544 * to resource contention.
545 */
546 Stats::Vector wbPenalized;
547 /** Number of instructions per cycle written back. */
548 Stats::Formula wbRate;
549 /** Average number of woken instructions per writeback. */
550 Stats::Formula wbFanout;
551 /** Number of instructions per cycle delayed in writing back . */
552 Stats::Formula wbPenalizedRate;
553};
554
555#endif // __CPU_O3_IEW_HH__
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