1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_IEW_HH__
32#define __CPU_O3_IEW_HH__
33
34#include <queue>
35
36#include "base/statistics.hh"
37#include "base/timebuf.hh"
38#include "config/full_system.hh"
39#include "cpu/o3/comm.hh"
40#include "cpu/o3/scoreboard.hh"
41#include "cpu/o3/lsq.hh"
42
43class DerivO3CPUParams;
44class FUPool;
45
46/**
47 * DefaultIEW handles both single threaded and SMT IEW
48 * (issue/execute/writeback). It handles the dispatching of
49 * instructions to the LSQ/IQ as part of the issue stage, and has the
50 * IQ try to issue instructions each cycle. The execute latency is
51 * actually tied into the issue latency to allow the IQ to be able to
52 * do back-to-back scheduling without having to speculatively schedule
53 * instructions. This happens by having the IQ have access to the
54 * functional units, and the IQ gets the execution latencies from the
55 * FUs when it issues instructions. Instructions reach the execute
56 * stage on the last cycle of their execution, which is when the IQ
57 * knows to wake up any dependent instructions, allowing back to back
58 * scheduling. The execute portion of IEW separates memory
59 * instructions from non-memory instructions, either telling the LSQ
60 * to execute the instruction, or executing the instruction directly.
61 * The writeback portion of IEW completes the instructions by waking
62 * up any dependents, and marking the register ready on the
63 * scoreboard.
64 */
65template<class Impl>
66class DefaultIEW
67{
68 private:
69 //Typedefs from Impl
70 typedef typename Impl::CPUPol CPUPol;
71 typedef typename Impl::DynInstPtr DynInstPtr;
72 typedef typename Impl::O3CPU O3CPU;
73
74 typedef typename CPUPol::IQ IQ;
75 typedef typename CPUPol::RenameMap RenameMap;
76 typedef typename CPUPol::LSQ LSQ;
77
78 typedef typename CPUPol::TimeStruct TimeStruct;
79 typedef typename CPUPol::IEWStruct IEWStruct;
80 typedef typename CPUPol::RenameStruct RenameStruct;
81 typedef typename CPUPol::IssueStruct IssueStruct;
82
83 friend class Impl::O3CPU;
84 friend class CPUPol::IQ;
85
86 public:
87 /** Overall IEW stage status. Used to determine if the CPU can
88 * deschedule itself due to a lack of activity.
89 */
90 enum Status {
91 Active,
92 Inactive
93 };
94
95 /** Status for Issue, Execute, and Writeback stages. */
96 enum StageStatus {
97 Running,
98 Blocked,
99 Idle,
100 StartSquash,
101 Squashing,
102 Unblocking
103 };
104
105 private:
106 /** Overall stage status. */
107 Status _status;
108 /** Dispatch status. */
109 StageStatus dispatchStatus[Impl::MaxThreads];
110 /** Execute status. */
111 StageStatus exeStatus;
112 /** Writeback status. */
113 StageStatus wbStatus;
114
115 public:
116 /** Constructs a DefaultIEW with the given parameters. */
117 DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params);
118
119 /** Returns the name of the DefaultIEW stage. */
120 std::string name() const;
121
122 /** Registers statistics. */
123 void regStats();
124
125 /** Initializes stage; sends back the number of free IQ and LSQ entries. */
126 void initStage();
127
128 /** Returns the dcache port. */
129 Port *getDcachePort() { return ldstQueue.getDcachePort(); }
130
131 /** Sets main time buffer used for backwards communication. */
132 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
133
134 /** Sets time buffer for getting instructions coming from rename. */
135 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
136
137 /** Sets time buffer to pass on instructions to commit. */
138 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
139
140 /** Sets pointer to list of active threads. */
141 void setActiveThreads(std::list<ThreadID> *at_ptr);
142
143 /** Sets pointer to the scoreboard. */
144 void setScoreboard(Scoreboard *sb_ptr);
145
146 /** Drains IEW stage. */
147 bool drain();
148
149 /** Resumes execution after a drain. */
150 void resume();
151
152 /** Completes switch out of IEW stage. */
153 void switchOut();
154
155 /** Takes over from another CPU's thread. */
156 void takeOverFrom();
157
158 /** Returns if IEW is switched out. */
159 bool isSwitchedOut() { return switchedOut; }
160
161 /** Squashes instructions in IEW for a specific thread. */
162 void squash(ThreadID tid);
163
164 /** Wakes all dependents of a completed instruction. */
165 void wakeDependents(DynInstPtr &inst);
166
167 /** Tells memory dependence unit that a memory instruction needs to be
168 * rescheduled. It will re-execute once replayMemInst() is called.
169 */
170 void rescheduleMemInst(DynInstPtr &inst);
171
172 /** Re-executes all rescheduled memory instructions. */
173 void replayMemInst(DynInstPtr &inst);
174
175 /** Sends an instruction to commit through the time buffer. */
176 void instToCommit(DynInstPtr &inst);
177
178 /** Inserts unused instructions of a thread into the skid buffer. */
179 void skidInsert(ThreadID tid);
180
181 /** Returns the max of the number of entries in all of the skid buffers. */
182 int skidCount();
183
184 /** Returns if all of the skid buffers are empty. */
185 bool skidsEmpty();
186
187 /** Updates overall IEW status based on all of the stages' statuses. */
188 void updateStatus();
189
190 /** Resets entries of the IQ and the LSQ. */
191 void resetEntries();
192
193 /** Tells the CPU to wakeup if it has descheduled itself due to no
194 * activity. Used mainly by the LdWritebackEvent.
195 */
196 void wakeCPU();
197
198 /** Reports to the CPU that there is activity this cycle. */
199 void activityThisCycle();
200
201 /** Tells CPU that the IEW stage is active and running. */
202 inline void activateStage();
203
204 /** Tells CPU that the IEW stage is inactive and idle. */
205 inline void deactivateStage();
206
207 /** Returns if the LSQ has any stores to writeback. */
208 bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
209
210 /** Returns if the LSQ has any stores to writeback. */
211 bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); }
212
213 void incrWb(InstSeqNum &sn)
214 {
215 if (++wbOutstanding == wbMax)
216 ableToIssue = false;
217 DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
218 assert(wbOutstanding <= wbMax);
219#ifdef DEBUG
220 wbList.insert(sn);
221#endif
222 }
223
224 void decrWb(InstSeqNum &sn)
225 {
226 if (wbOutstanding-- == wbMax)
227 ableToIssue = true;
228 DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
229 assert(wbOutstanding >= 0);
230#ifdef DEBUG
231 assert(wbList.find(sn) != wbList.end());
232 wbList.erase(sn);
233#endif
234 }
235
236#ifdef DEBUG
237 std::set<InstSeqNum> wbList;
238
239 void dumpWb()
240 {
241 std::set<InstSeqNum>::iterator wb_it = wbList.begin();
242 while (wb_it != wbList.end()) {
243 cprintf("[sn:%lli]\n",
244 (*wb_it));
245 wb_it++;
246 }
247 }
248#endif
249
250 bool canIssue() { return ableToIssue; }
251
252 bool ableToIssue;
253
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_IEW_HH__
32#define __CPU_O3_IEW_HH__
33
34#include <queue>
35
36#include "base/statistics.hh"
37#include "base/timebuf.hh"
38#include "config/full_system.hh"
39#include "cpu/o3/comm.hh"
40#include "cpu/o3/scoreboard.hh"
41#include "cpu/o3/lsq.hh"
42
43class DerivO3CPUParams;
44class FUPool;
45
46/**
47 * DefaultIEW handles both single threaded and SMT IEW
48 * (issue/execute/writeback). It handles the dispatching of
49 * instructions to the LSQ/IQ as part of the issue stage, and has the
50 * IQ try to issue instructions each cycle. The execute latency is
51 * actually tied into the issue latency to allow the IQ to be able to
52 * do back-to-back scheduling without having to speculatively schedule
53 * instructions. This happens by having the IQ have access to the
54 * functional units, and the IQ gets the execution latencies from the
55 * FUs when it issues instructions. Instructions reach the execute
56 * stage on the last cycle of their execution, which is when the IQ
57 * knows to wake up any dependent instructions, allowing back to back
58 * scheduling. The execute portion of IEW separates memory
59 * instructions from non-memory instructions, either telling the LSQ
60 * to execute the instruction, or executing the instruction directly.
61 * The writeback portion of IEW completes the instructions by waking
62 * up any dependents, and marking the register ready on the
63 * scoreboard.
64 */
65template<class Impl>
66class DefaultIEW
67{
68 private:
69 //Typedefs from Impl
70 typedef typename Impl::CPUPol CPUPol;
71 typedef typename Impl::DynInstPtr DynInstPtr;
72 typedef typename Impl::O3CPU O3CPU;
73
74 typedef typename CPUPol::IQ IQ;
75 typedef typename CPUPol::RenameMap RenameMap;
76 typedef typename CPUPol::LSQ LSQ;
77
78 typedef typename CPUPol::TimeStruct TimeStruct;
79 typedef typename CPUPol::IEWStruct IEWStruct;
80 typedef typename CPUPol::RenameStruct RenameStruct;
81 typedef typename CPUPol::IssueStruct IssueStruct;
82
83 friend class Impl::O3CPU;
84 friend class CPUPol::IQ;
85
86 public:
87 /** Overall IEW stage status. Used to determine if the CPU can
88 * deschedule itself due to a lack of activity.
89 */
90 enum Status {
91 Active,
92 Inactive
93 };
94
95 /** Status for Issue, Execute, and Writeback stages. */
96 enum StageStatus {
97 Running,
98 Blocked,
99 Idle,
100 StartSquash,
101 Squashing,
102 Unblocking
103 };
104
105 private:
106 /** Overall stage status. */
107 Status _status;
108 /** Dispatch status. */
109 StageStatus dispatchStatus[Impl::MaxThreads];
110 /** Execute status. */
111 StageStatus exeStatus;
112 /** Writeback status. */
113 StageStatus wbStatus;
114
115 public:
116 /** Constructs a DefaultIEW with the given parameters. */
117 DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params);
118
119 /** Returns the name of the DefaultIEW stage. */
120 std::string name() const;
121
122 /** Registers statistics. */
123 void regStats();
124
125 /** Initializes stage; sends back the number of free IQ and LSQ entries. */
126 void initStage();
127
128 /** Returns the dcache port. */
129 Port *getDcachePort() { return ldstQueue.getDcachePort(); }
130
131 /** Sets main time buffer used for backwards communication. */
132 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
133
134 /** Sets time buffer for getting instructions coming from rename. */
135 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
136
137 /** Sets time buffer to pass on instructions to commit. */
138 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
139
140 /** Sets pointer to list of active threads. */
141 void setActiveThreads(std::list<ThreadID> *at_ptr);
142
143 /** Sets pointer to the scoreboard. */
144 void setScoreboard(Scoreboard *sb_ptr);
145
146 /** Drains IEW stage. */
147 bool drain();
148
149 /** Resumes execution after a drain. */
150 void resume();
151
152 /** Completes switch out of IEW stage. */
153 void switchOut();
154
155 /** Takes over from another CPU's thread. */
156 void takeOverFrom();
157
158 /** Returns if IEW is switched out. */
159 bool isSwitchedOut() { return switchedOut; }
160
161 /** Squashes instructions in IEW for a specific thread. */
162 void squash(ThreadID tid);
163
164 /** Wakes all dependents of a completed instruction. */
165 void wakeDependents(DynInstPtr &inst);
166
167 /** Tells memory dependence unit that a memory instruction needs to be
168 * rescheduled. It will re-execute once replayMemInst() is called.
169 */
170 void rescheduleMemInst(DynInstPtr &inst);
171
172 /** Re-executes all rescheduled memory instructions. */
173 void replayMemInst(DynInstPtr &inst);
174
175 /** Sends an instruction to commit through the time buffer. */
176 void instToCommit(DynInstPtr &inst);
177
178 /** Inserts unused instructions of a thread into the skid buffer. */
179 void skidInsert(ThreadID tid);
180
181 /** Returns the max of the number of entries in all of the skid buffers. */
182 int skidCount();
183
184 /** Returns if all of the skid buffers are empty. */
185 bool skidsEmpty();
186
187 /** Updates overall IEW status based on all of the stages' statuses. */
188 void updateStatus();
189
190 /** Resets entries of the IQ and the LSQ. */
191 void resetEntries();
192
193 /** Tells the CPU to wakeup if it has descheduled itself due to no
194 * activity. Used mainly by the LdWritebackEvent.
195 */
196 void wakeCPU();
197
198 /** Reports to the CPU that there is activity this cycle. */
199 void activityThisCycle();
200
201 /** Tells CPU that the IEW stage is active and running. */
202 inline void activateStage();
203
204 /** Tells CPU that the IEW stage is inactive and idle. */
205 inline void deactivateStage();
206
207 /** Returns if the LSQ has any stores to writeback. */
208 bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
209
210 /** Returns if the LSQ has any stores to writeback. */
211 bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); }
212
213 void incrWb(InstSeqNum &sn)
214 {
215 if (++wbOutstanding == wbMax)
216 ableToIssue = false;
217 DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
218 assert(wbOutstanding <= wbMax);
219#ifdef DEBUG
220 wbList.insert(sn);
221#endif
222 }
223
224 void decrWb(InstSeqNum &sn)
225 {
226 if (wbOutstanding-- == wbMax)
227 ableToIssue = true;
228 DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
229 assert(wbOutstanding >= 0);
230#ifdef DEBUG
231 assert(wbList.find(sn) != wbList.end());
232 wbList.erase(sn);
233#endif
234 }
235
236#ifdef DEBUG
237 std::set<InstSeqNum> wbList;
238
239 void dumpWb()
240 {
241 std::set<InstSeqNum>::iterator wb_it = wbList.begin();
242 while (wb_it != wbList.end()) {
243 cprintf("[sn:%lli]\n",
244 (*wb_it));
245 wb_it++;
246 }
247 }
248#endif
249
250 bool canIssue() { return ableToIssue; }
251
252 bool ableToIssue;
253
|
254 private:
255 /** Sends commit proper information for a squash due to a branch
256 * mispredict.
257 */
258 void squashDueToBranch(DynInstPtr &inst, ThreadID tid);
259
260 /** Sends commit proper information for a squash due to a memory order
261 * violation.
262 */
263 void squashDueToMemOrder(DynInstPtr &inst, ThreadID tid);
264
265 /** Sends commit proper information for a squash due to memory becoming
266 * blocked (younger issued instructions must be retried).
267 */
268 void squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid);
269
270 /** Sets Dispatch to blocked, and signals back to other stages to block. */
271 void block(ThreadID tid);
272
273 /** Unblocks Dispatch if the skid buffer is empty, and signals back to
274 * other stages to unblock.
275 */
276 void unblock(ThreadID tid);
277
278 /** Determines proper actions to take given Dispatch's status. */
279 void dispatch(ThreadID tid);
280
281 /** Dispatches instructions to IQ and LSQ. */
282 void dispatchInsts(ThreadID tid);
283
284 /** Executes instructions. In the case of memory operations, it informs the
285 * LSQ to execute the instructions. Also handles any redirects that occur
286 * due to the executed instructions.
287 */
288 void executeInsts();
289
290 /** Writebacks instructions. In our model, the instruction's execute()
291 * function atomically reads registers, executes, and writes registers.
292 * Thus this writeback only wakes up dependent instructions, and informs
293 * the scoreboard of registers becoming ready.
294 */
295 void writebackInsts();
296
297 /** Returns the number of valid, non-squashed instructions coming from
298 * rename to dispatch.
299 */
300 unsigned validInstsFromRename();
301
302 /** Reads the stall signals. */
303 void readStallSignals(ThreadID tid);
304
305 /** Checks if any of the stall conditions are currently true. */
306 bool checkStall(ThreadID tid);
307
308 /** Processes inputs and changes state accordingly. */
309 void checkSignalsAndUpdate(ThreadID tid);
310
311 /** Removes instructions from rename from a thread's instruction list. */
312 void emptyRenameInsts(ThreadID tid);
313
314 /** Sorts instructions coming from rename into lists separated by thread. */
315 void sortInsts();
316
317 public:
318 /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and
319 * Writeback to run for one cycle.
320 */
321 void tick();
322
323 private:
324 /** Updates execution stats based on the instruction. */
325 void updateExeInstStats(DynInstPtr &inst);
326
327 /** Pointer to main time buffer used for backwards communication. */
328 TimeBuffer<TimeStruct> *timeBuffer;
329
330 /** Wire to write information heading to previous stages. */
331 typename TimeBuffer<TimeStruct>::wire toFetch;
332
333 /** Wire to get commit's output from backwards time buffer. */
334 typename TimeBuffer<TimeStruct>::wire fromCommit;
335
336 /** Wire to write information heading to previous stages. */
337 typename TimeBuffer<TimeStruct>::wire toRename;
338
339 /** Rename instruction queue interface. */
340 TimeBuffer<RenameStruct> *renameQueue;
341
342 /** Wire to get rename's output from rename queue. */
343 typename TimeBuffer<RenameStruct>::wire fromRename;
344
345 /** Issue stage queue. */
346 TimeBuffer<IssueStruct> issueToExecQueue;
347
348 /** Wire to read information from the issue stage time queue. */
349 typename TimeBuffer<IssueStruct>::wire fromIssue;
350
351 /**
352 * IEW stage time buffer. Holds ROB indices of instructions that
353 * can be marked as completed.
354 */
355 TimeBuffer<IEWStruct> *iewQueue;
356
357 /** Wire to write infromation heading to commit. */
358 typename TimeBuffer<IEWStruct>::wire toCommit;
359
360 /** Queue of all instructions coming from rename this cycle. */
361 std::queue<DynInstPtr> insts[Impl::MaxThreads];
362
363 /** Skid buffer between rename and IEW. */
364 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
365
366 /** Scoreboard pointer. */
367 Scoreboard* scoreboard;
368
369 private:
370 /** CPU pointer. */
371 O3CPU *cpu;
372
373 /** Records if IEW has written to the time buffer this cycle, so that the
374 * CPU can deschedule itself if there is no activity.
375 */
376 bool wroteToTimeBuffer;
377
378 /** Source of possible stalls. */
379 struct Stalls {
380 bool commit;
381 };
382
383 /** Stages that are telling IEW to stall. */
384 Stalls stalls[Impl::MaxThreads];
385
386 /** Debug function to print instructions that are issued this cycle. */
387 void printAvailableInsts();
388
389 public:
390 /** Instruction queue. */
391 IQ instQueue;
392
393 /** Load / store queue. */
394 LSQ ldstQueue;
395
396 /** Pointer to the functional unit pool. */
397 FUPool *fuPool;
398 /** Records if the LSQ needs to be updated on the next cycle, so that
399 * IEW knows if there will be activity on the next cycle.
400 */
401 bool updateLSQNextCycle;
402
403 private:
404 /** Records if there is a fetch redirect on this cycle for each thread. */
405 bool fetchRedirect[Impl::MaxThreads];
406
407 /** Records if the queues have been changed (inserted or issued insts),
408 * so that IEW knows to broadcast the updated amount of free entries.
409 */
410 bool updatedQueues;
411
412 /** Commit to IEW delay, in ticks. */
413 unsigned commitToIEWDelay;
414
415 /** Rename to IEW delay, in ticks. */
416 unsigned renameToIEWDelay;
417
418 /**
419 * Issue to execute delay, in ticks. What this actually represents is
420 * the amount of time it takes for an instruction to wake up, be
421 * scheduled, and sent to a FU for execution.
422 */
423 unsigned issueToExecuteDelay;
424
425 /** Width of dispatch, in instructions. */
426 unsigned dispatchWidth;
427
428 /** Width of issue, in instructions. */
429 unsigned issueWidth;
430
431 /** Index into queue of instructions being written back. */
432 unsigned wbNumInst;
433
434 /** Cycle number within the queue of instructions being written back.
435 * Used in case there are too many instructions writing back at the current
436 * cycle and writesbacks need to be scheduled for the future. See comments
437 * in instToCommit().
438 */
439 unsigned wbCycle;
440
441 /** Number of instructions in flight that will writeback. */
442
443 /** Number of instructions in flight that will writeback. */
444 int wbOutstanding;
445
446 /** Writeback width. */
447 unsigned wbWidth;
448
449 /** Writeback width * writeback depth, where writeback depth is
450 * the number of cycles of writing back instructions that can be
451 * buffered. */
452 unsigned wbMax;
453
454 /** Number of active threads. */
455 ThreadID numThreads;
456
457 /** Pointer to list of active threads. */
458 std::list<ThreadID> *activeThreads;
459
460 /** Maximum size of the skid buffer. */
461 unsigned skidBufferMax;
462
463 /** Is this stage switched out. */
464 bool switchedOut;
465
466 /** Stat for total number of idle cycles. */
467 Stats::Scalar iewIdleCycles;
468 /** Stat for total number of squashing cycles. */
469 Stats::Scalar iewSquashCycles;
470 /** Stat for total number of blocking cycles. */
471 Stats::Scalar iewBlockCycles;
472 /** Stat for total number of unblocking cycles. */
473 Stats::Scalar iewUnblockCycles;
474 /** Stat for total number of instructions dispatched. */
475 Stats::Scalar iewDispatchedInsts;
476 /** Stat for total number of squashed instructions dispatch skips. */
477 Stats::Scalar iewDispSquashedInsts;
478 /** Stat for total number of dispatched load instructions. */
479 Stats::Scalar iewDispLoadInsts;
480 /** Stat for total number of dispatched store instructions. */
481 Stats::Scalar iewDispStoreInsts;
482 /** Stat for total number of dispatched non speculative instructions. */
483 Stats::Scalar iewDispNonSpecInsts;
484 /** Stat for number of times the IQ becomes full. */
485 Stats::Scalar iewIQFullEvents;
486 /** Stat for number of times the LSQ becomes full. */
487 Stats::Scalar iewLSQFullEvents;
488 /** Stat for total number of memory ordering violation events. */
489 Stats::Scalar memOrderViolationEvents;
490 /** Stat for total number of incorrect predicted taken branches. */
491 Stats::Scalar predictedTakenIncorrect;
492 /** Stat for total number of incorrect predicted not taken branches. */
493 Stats::Scalar predictedNotTakenIncorrect;
494 /** Stat for total number of mispredicted branches detected at execute. */
495 Stats::Formula branchMispredicts;
496
497 /** Stat for total number of executed instructions. */
498 Stats::Scalar iewExecutedInsts;
499 /** Stat for total number of executed load instructions. */
500 Stats::Vector iewExecLoadInsts;
501 /** Stat for total number of executed store instructions. */
502// Stats::Scalar iewExecStoreInsts;
503 /** Stat for total number of squashed instructions skipped at execute. */
504 Stats::Scalar iewExecSquashedInsts;
505 /** Number of executed software prefetches. */
506 Stats::Vector iewExecutedSwp;
507 /** Number of executed nops. */
508 Stats::Vector iewExecutedNop;
509 /** Number of executed meomory references. */
510 Stats::Vector iewExecutedRefs;
511 /** Number of executed branches. */
512 Stats::Vector iewExecutedBranches;
513 /** Number of executed store instructions. */
514 Stats::Formula iewExecStoreInsts;
515 /** Number of instructions executed per cycle. */
516 Stats::Formula iewExecRate;
517
518 /** Number of instructions sent to commit. */
519 Stats::Vector iewInstsToCommit;
520 /** Number of instructions that writeback. */
521 Stats::Vector writebackCount;
522 /** Number of instructions that wake consumers. */
523 Stats::Vector producerInst;
524 /** Number of instructions that wake up from producers. */
525 Stats::Vector consumerInst;
526 /** Number of instructions that were delayed in writing back due
527 * to resource contention.
528 */
529 Stats::Vector wbPenalized;
530 /** Number of instructions per cycle written back. */
531 Stats::Formula wbRate;
532 /** Average number of woken instructions per writeback. */
533 Stats::Formula wbFanout;
534 /** Number of instructions per cycle delayed in writing back . */
535 Stats::Formula wbPenalizedRate;
536};
537
538#endif // __CPU_O3_IEW_HH__
| 257 private:
258 /** Sends commit proper information for a squash due to a branch
259 * mispredict.
260 */
261 void squashDueToBranch(DynInstPtr &inst, ThreadID tid);
262
263 /** Sends commit proper information for a squash due to a memory order
264 * violation.
265 */
266 void squashDueToMemOrder(DynInstPtr &inst, ThreadID tid);
267
268 /** Sends commit proper information for a squash due to memory becoming
269 * blocked (younger issued instructions must be retried).
270 */
271 void squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid);
272
273 /** Sets Dispatch to blocked, and signals back to other stages to block. */
274 void block(ThreadID tid);
275
276 /** Unblocks Dispatch if the skid buffer is empty, and signals back to
277 * other stages to unblock.
278 */
279 void unblock(ThreadID tid);
280
281 /** Determines proper actions to take given Dispatch's status. */
282 void dispatch(ThreadID tid);
283
284 /** Dispatches instructions to IQ and LSQ. */
285 void dispatchInsts(ThreadID tid);
286
287 /** Executes instructions. In the case of memory operations, it informs the
288 * LSQ to execute the instructions. Also handles any redirects that occur
289 * due to the executed instructions.
290 */
291 void executeInsts();
292
293 /** Writebacks instructions. In our model, the instruction's execute()
294 * function atomically reads registers, executes, and writes registers.
295 * Thus this writeback only wakes up dependent instructions, and informs
296 * the scoreboard of registers becoming ready.
297 */
298 void writebackInsts();
299
300 /** Returns the number of valid, non-squashed instructions coming from
301 * rename to dispatch.
302 */
303 unsigned validInstsFromRename();
304
305 /** Reads the stall signals. */
306 void readStallSignals(ThreadID tid);
307
308 /** Checks if any of the stall conditions are currently true. */
309 bool checkStall(ThreadID tid);
310
311 /** Processes inputs and changes state accordingly. */
312 void checkSignalsAndUpdate(ThreadID tid);
313
314 /** Removes instructions from rename from a thread's instruction list. */
315 void emptyRenameInsts(ThreadID tid);
316
317 /** Sorts instructions coming from rename into lists separated by thread. */
318 void sortInsts();
319
320 public:
321 /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and
322 * Writeback to run for one cycle.
323 */
324 void tick();
325
326 private:
327 /** Updates execution stats based on the instruction. */
328 void updateExeInstStats(DynInstPtr &inst);
329
330 /** Pointer to main time buffer used for backwards communication. */
331 TimeBuffer<TimeStruct> *timeBuffer;
332
333 /** Wire to write information heading to previous stages. */
334 typename TimeBuffer<TimeStruct>::wire toFetch;
335
336 /** Wire to get commit's output from backwards time buffer. */
337 typename TimeBuffer<TimeStruct>::wire fromCommit;
338
339 /** Wire to write information heading to previous stages. */
340 typename TimeBuffer<TimeStruct>::wire toRename;
341
342 /** Rename instruction queue interface. */
343 TimeBuffer<RenameStruct> *renameQueue;
344
345 /** Wire to get rename's output from rename queue. */
346 typename TimeBuffer<RenameStruct>::wire fromRename;
347
348 /** Issue stage queue. */
349 TimeBuffer<IssueStruct> issueToExecQueue;
350
351 /** Wire to read information from the issue stage time queue. */
352 typename TimeBuffer<IssueStruct>::wire fromIssue;
353
354 /**
355 * IEW stage time buffer. Holds ROB indices of instructions that
356 * can be marked as completed.
357 */
358 TimeBuffer<IEWStruct> *iewQueue;
359
360 /** Wire to write infromation heading to commit. */
361 typename TimeBuffer<IEWStruct>::wire toCommit;
362
363 /** Queue of all instructions coming from rename this cycle. */
364 std::queue<DynInstPtr> insts[Impl::MaxThreads];
365
366 /** Skid buffer between rename and IEW. */
367 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
368
369 /** Scoreboard pointer. */
370 Scoreboard* scoreboard;
371
372 private:
373 /** CPU pointer. */
374 O3CPU *cpu;
375
376 /** Records if IEW has written to the time buffer this cycle, so that the
377 * CPU can deschedule itself if there is no activity.
378 */
379 bool wroteToTimeBuffer;
380
381 /** Source of possible stalls. */
382 struct Stalls {
383 bool commit;
384 };
385
386 /** Stages that are telling IEW to stall. */
387 Stalls stalls[Impl::MaxThreads];
388
389 /** Debug function to print instructions that are issued this cycle. */
390 void printAvailableInsts();
391
392 public:
393 /** Instruction queue. */
394 IQ instQueue;
395
396 /** Load / store queue. */
397 LSQ ldstQueue;
398
399 /** Pointer to the functional unit pool. */
400 FUPool *fuPool;
401 /** Records if the LSQ needs to be updated on the next cycle, so that
402 * IEW knows if there will be activity on the next cycle.
403 */
404 bool updateLSQNextCycle;
405
406 private:
407 /** Records if there is a fetch redirect on this cycle for each thread. */
408 bool fetchRedirect[Impl::MaxThreads];
409
410 /** Records if the queues have been changed (inserted or issued insts),
411 * so that IEW knows to broadcast the updated amount of free entries.
412 */
413 bool updatedQueues;
414
415 /** Commit to IEW delay, in ticks. */
416 unsigned commitToIEWDelay;
417
418 /** Rename to IEW delay, in ticks. */
419 unsigned renameToIEWDelay;
420
421 /**
422 * Issue to execute delay, in ticks. What this actually represents is
423 * the amount of time it takes for an instruction to wake up, be
424 * scheduled, and sent to a FU for execution.
425 */
426 unsigned issueToExecuteDelay;
427
428 /** Width of dispatch, in instructions. */
429 unsigned dispatchWidth;
430
431 /** Width of issue, in instructions. */
432 unsigned issueWidth;
433
434 /** Index into queue of instructions being written back. */
435 unsigned wbNumInst;
436
437 /** Cycle number within the queue of instructions being written back.
438 * Used in case there are too many instructions writing back at the current
439 * cycle and writesbacks need to be scheduled for the future. See comments
440 * in instToCommit().
441 */
442 unsigned wbCycle;
443
444 /** Number of instructions in flight that will writeback. */
445
446 /** Number of instructions in flight that will writeback. */
447 int wbOutstanding;
448
449 /** Writeback width. */
450 unsigned wbWidth;
451
452 /** Writeback width * writeback depth, where writeback depth is
453 * the number of cycles of writing back instructions that can be
454 * buffered. */
455 unsigned wbMax;
456
457 /** Number of active threads. */
458 ThreadID numThreads;
459
460 /** Pointer to list of active threads. */
461 std::list<ThreadID> *activeThreads;
462
463 /** Maximum size of the skid buffer. */
464 unsigned skidBufferMax;
465
466 /** Is this stage switched out. */
467 bool switchedOut;
468
469 /** Stat for total number of idle cycles. */
470 Stats::Scalar iewIdleCycles;
471 /** Stat for total number of squashing cycles. */
472 Stats::Scalar iewSquashCycles;
473 /** Stat for total number of blocking cycles. */
474 Stats::Scalar iewBlockCycles;
475 /** Stat for total number of unblocking cycles. */
476 Stats::Scalar iewUnblockCycles;
477 /** Stat for total number of instructions dispatched. */
478 Stats::Scalar iewDispatchedInsts;
479 /** Stat for total number of squashed instructions dispatch skips. */
480 Stats::Scalar iewDispSquashedInsts;
481 /** Stat for total number of dispatched load instructions. */
482 Stats::Scalar iewDispLoadInsts;
483 /** Stat for total number of dispatched store instructions. */
484 Stats::Scalar iewDispStoreInsts;
485 /** Stat for total number of dispatched non speculative instructions. */
486 Stats::Scalar iewDispNonSpecInsts;
487 /** Stat for number of times the IQ becomes full. */
488 Stats::Scalar iewIQFullEvents;
489 /** Stat for number of times the LSQ becomes full. */
490 Stats::Scalar iewLSQFullEvents;
491 /** Stat for total number of memory ordering violation events. */
492 Stats::Scalar memOrderViolationEvents;
493 /** Stat for total number of incorrect predicted taken branches. */
494 Stats::Scalar predictedTakenIncorrect;
495 /** Stat for total number of incorrect predicted not taken branches. */
496 Stats::Scalar predictedNotTakenIncorrect;
497 /** Stat for total number of mispredicted branches detected at execute. */
498 Stats::Formula branchMispredicts;
499
500 /** Stat for total number of executed instructions. */
501 Stats::Scalar iewExecutedInsts;
502 /** Stat for total number of executed load instructions. */
503 Stats::Vector iewExecLoadInsts;
504 /** Stat for total number of executed store instructions. */
505// Stats::Scalar iewExecStoreInsts;
506 /** Stat for total number of squashed instructions skipped at execute. */
507 Stats::Scalar iewExecSquashedInsts;
508 /** Number of executed software prefetches. */
509 Stats::Vector iewExecutedSwp;
510 /** Number of executed nops. */
511 Stats::Vector iewExecutedNop;
512 /** Number of executed meomory references. */
513 Stats::Vector iewExecutedRefs;
514 /** Number of executed branches. */
515 Stats::Vector iewExecutedBranches;
516 /** Number of executed store instructions. */
517 Stats::Formula iewExecStoreInsts;
518 /** Number of instructions executed per cycle. */
519 Stats::Formula iewExecRate;
520
521 /** Number of instructions sent to commit. */
522 Stats::Vector iewInstsToCommit;
523 /** Number of instructions that writeback. */
524 Stats::Vector writebackCount;
525 /** Number of instructions that wake consumers. */
526 Stats::Vector producerInst;
527 /** Number of instructions that wake up from producers. */
528 Stats::Vector consumerInst;
529 /** Number of instructions that were delayed in writing back due
530 * to resource contention.
531 */
532 Stats::Vector wbPenalized;
533 /** Number of instructions per cycle written back. */
534 Stats::Formula wbRate;
535 /** Average number of woken instructions per writeback. */
536 Stats::Formula wbFanout;
537 /** Number of instructions per cycle delayed in writing back . */
538 Stats::Formula wbPenalizedRate;
539};
540
541#endif // __CPU_O3_IEW_HH__
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