1/*
| 1/*
|
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
| 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
|
3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
| 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
27 * 28 * Authors: Kevin Lim
| |
29 */ 30
| 27 */ 28
|
31//Todo: Update with statuses. 32//Need to handle delaying writes to the writeback bus if it's full at the 33//given time.
| 29#ifndef __CPU_O3_IEW_HH__ 30#define __CPU_O3_IEW_HH__
|
34
| 31
|
35#ifndef __CPU_O3_CPU_SIMPLE_IEW_HH__ 36#define __CPU_O3_CPU_SIMPLE_IEW_HH__ 37
| |
38#include <queue> 39
| 32#include <queue> 33
|
40#include "config/full_system.hh"
| |
41#include "base/statistics.hh" 42#include "base/timebuf.hh"
| 34#include "base/statistics.hh" 35#include "base/timebuf.hh"
|
| 36#include "config/full_system.hh"
|
43#include "cpu/o3/comm.hh"
| 37#include "cpu/o3/comm.hh"
|
| 38#include "cpu/o3/scoreboard.hh" 39#include "cpu/o3/lsq.hh"
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44
| 40
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| 41class FUPool; 42 43/** 44 * DefaultIEW handles both single threaded and SMT IEW 45 * (issue/execute/writeback). It handles the dispatching of 46 * instructions to the LSQ/IQ as part of the issue stage, and has the 47 * IQ try to issue instructions each cycle. The execute latency is 48 * actually tied into the issue latency to allow the IQ to be able to 49 * do back-to-back scheduling without having to speculatively schedule 50 * instructions. This happens by having the IQ have access to the 51 * functional units, and the IQ gets the execution latencies from the 52 * FUs when it issues instructions. Instructions reach the execute 53 * stage on the last cycle of their execution, which is when the IQ 54 * knows to wake up any dependent instructions, allowing back to back 55 * scheduling. The execute portion of IEW separates memory 56 * instructions from non-memory instructions, either telling the LSQ 57 * to execute the instruction, or executing the instruction directly. 58 * The writeback portion of IEW completes the instructions by waking 59 * up any dependents, and marking the register ready on the 60 * scoreboard. 61 */
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45template<class Impl>
| 62template<class Impl>
|
46class SimpleIEW
| 63class DefaultIEW
|
47{ 48 private: 49 //Typedefs from Impl 50 typedef typename Impl::CPUPol CPUPol; 51 typedef typename Impl::DynInstPtr DynInstPtr; 52 typedef typename Impl::FullCPU FullCPU; 53 typedef typename Impl::Params Params; 54 55 typedef typename CPUPol::IQ IQ; 56 typedef typename CPUPol::RenameMap RenameMap;
| 64{ 65 private: 66 //Typedefs from Impl 67 typedef typename Impl::CPUPol CPUPol; 68 typedef typename Impl::DynInstPtr DynInstPtr; 69 typedef typename Impl::FullCPU FullCPU; 70 typedef typename Impl::Params Params; 71 72 typedef typename CPUPol::IQ IQ; 73 typedef typename CPUPol::RenameMap RenameMap;
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57 typedef typename CPUPol::LDSTQ LDSTQ;
| 74 typedef typename CPUPol::LSQ LSQ;
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58 59 typedef typename CPUPol::TimeStruct TimeStruct; 60 typedef typename CPUPol::IEWStruct IEWStruct; 61 typedef typename CPUPol::RenameStruct RenameStruct; 62 typedef typename CPUPol::IssueStruct IssueStruct; 63 64 friend class Impl::FullCPU;
| 75 76 typedef typename CPUPol::TimeStruct TimeStruct; 77 typedef typename CPUPol::IEWStruct IEWStruct; 78 typedef typename CPUPol::RenameStruct RenameStruct; 79 typedef typename CPUPol::IssueStruct IssueStruct; 80 81 friend class Impl::FullCPU;
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| 82 friend class CPUPol::IQ; 83
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65 public:
| 84 public:
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| 85 /** Overall IEW stage status. Used to determine if the CPU can 86 * deschedule itself due to a lack of activity. 87 */
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66 enum Status {
| 88 enum Status {
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| 89 Active, 90 Inactive 91 }; 92 93 /** Status for Issue, Execute, and Writeback stages. */ 94 enum StageStatus {
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67 Running, 68 Blocked, 69 Idle,
| 95 Running, 96 Blocked, 97 Idle,
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| 98 StartSquash,
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70 Squashing, 71 Unblocking 72 }; 73 74 private:
| 99 Squashing, 100 Unblocking 101 }; 102 103 private:
|
| 104 /** Overall stage status. */
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75 Status _status;
| 105 Status _status;
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76 Status _issueStatus; 77 Status _exeStatus; 78 Status _wbStatus;
| 106 /** Dispatch status. */ 107 StageStatus dispatchStatus[Impl::MaxThreads]; 108 /** Execute status. */ 109 StageStatus exeStatus; 110 /** Writeback status. */ 111 StageStatus wbStatus;
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79 80 public:
| 112 113 public:
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81 class WritebackEvent : public Event { 82 private: 83 DynInstPtr inst; 84 SimpleIEW<Impl> *iewStage;
| 114 /** Constructs a DefaultIEW with the given parameters. */ 115 DefaultIEW(Params *params);
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85
| 116
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86 public: 87 WritebackEvent(DynInstPtr &_inst, SimpleIEW<Impl> *_iew);
| 117 /** Returns the name of the DefaultIEW stage. */ 118 std::string name() const;
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88
| 119
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89 virtual void process(); 90 virtual const char *description(); 91 }; 92 93 public: 94 SimpleIEW(Params ¶ms); 95
| 120 /** Registers statistics. */
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96 void regStats(); 97
| 121 void regStats(); 122
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| 123 /** Initializes stage; sends back the number of free IQ and LSQ entries. */ 124 void initStage(); 125 126 /** Sets CPU pointer for IEW, IQ, and LSQ. */
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98 void setCPU(FullCPU *cpu_ptr); 99
| 127 void setCPU(FullCPU *cpu_ptr); 128
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| 129 /** Sets main time buffer used for backwards communication. */
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100 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 101
| 130 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 131
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| 132 /** Sets time buffer for getting instructions coming from rename. */
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102 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 103
| 133 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 134
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| 135 /** Sets time buffer to pass on instructions to commit. */
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104 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 105
| 136 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 137
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106 void setRenameMap(RenameMap *rm_ptr);
| 138 /** Sets pointer to list of active threads. */ 139 void setActiveThreads(std::list<unsigned> *at_ptr);
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107
| 140
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108 void squash();
| 141 /** Sets pointer to the scoreboard. */ 142 void setScoreboard(Scoreboard *sb_ptr);
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109
| 143
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110 void squashDueToBranch(DynInstPtr &inst);
| 144 void switchOut();
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111
| 145
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112 void squashDueToMem(DynInstPtr &inst);
| 146 void doSwitchOut();
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113
| 147
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114 void block();
| 148 void takeOverFrom();
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115
| 149
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116 inline void unblock();
| 150 bool isSwitchedOut() { return switchedOut; }
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117
| 151
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| 152 /** Sets page table pointer within LSQ. */ 153// void setPageTable(PageTable *pt_ptr); 154 155 /** Squashes instructions in IEW for a specific thread. */ 156 void squash(unsigned tid); 157 158 /** Wakes all dependents of a completed instruction. */
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118 void wakeDependents(DynInstPtr &inst); 119
| 159 void wakeDependents(DynInstPtr &inst); 160
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| 161 /** Tells memory dependence unit that a memory instruction needs to be 162 * rescheduled. It will re-execute once replayMemInst() is called. 163 */ 164 void rescheduleMemInst(DynInstPtr &inst); 165 166 /** Re-executes all rescheduled memory instructions. */ 167 void replayMemInst(DynInstPtr &inst); 168 169 /** Sends an instruction to commit through the time buffer. */
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120 void instToCommit(DynInstPtr &inst); 121
| 170 void instToCommit(DynInstPtr &inst); 171
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| 172 /** Inserts unused instructions of a thread into the skid buffer. */ 173 void skidInsert(unsigned tid); 174 175 /** Returns the max of the number of entries in all of the skid buffers. */ 176 int skidCount(); 177 178 /** Returns if all of the skid buffers are empty. */ 179 bool skidsEmpty(); 180 181 /** Updates overall IEW status based on all of the stages' statuses. */ 182 void updateStatus(); 183 184 /** Resets entries of the IQ and the LSQ. */ 185 void resetEntries(); 186 187 /** Tells the CPU to wakeup if it has descheduled itself due to no 188 * activity. Used mainly by the LdWritebackEvent. 189 */ 190 void wakeCPU(); 191 192 /** Reports to the CPU that there is activity this cycle. */ 193 void activityThisCycle(); 194 195 /** Tells CPU that the IEW stage is active and running. */ 196 inline void activateStage(); 197 198 /** Tells CPU that the IEW stage is inactive and idle. */ 199 inline void deactivateStage(); 200 201 /** Returns if the LSQ has any stores to writeback. */ 202 bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); } 203
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122 private:
| 204 private:
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123 void dispatchInsts();
| 205 /** Sends commit proper information for a squash due to a branch 206 * mispredict. 207 */ 208 void squashDueToBranch(DynInstPtr &inst, unsigned thread_id);
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124
| 209
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| 210 /** Sends commit proper information for a squash due to a memory order 211 * violation. 212 */ 213 void squashDueToMemOrder(DynInstPtr &inst, unsigned thread_id); 214 215 /** Sends commit proper information for a squash due to memory becoming 216 * blocked (younger issued instructions must be retried). 217 */ 218 void squashDueToMemBlocked(DynInstPtr &inst, unsigned thread_id); 219 220 /** Sets Dispatch to blocked, and signals back to other stages to block. */ 221 void block(unsigned thread_id); 222 223 /** Unblocks Dispatch if the skid buffer is empty, and signals back to 224 * other stages to unblock. 225 */ 226 void unblock(unsigned thread_id); 227 228 /** Determines proper actions to take given Dispatch's status. */ 229 void dispatch(unsigned tid); 230 231 /** Dispatches instructions to IQ and LSQ. */ 232 void dispatchInsts(unsigned tid); 233 234 /** Executes instructions. In the case of memory operations, it informs the 235 * LSQ to execute the instructions. Also handles any redirects that occur 236 * due to the executed instructions. 237 */
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125 void executeInsts(); 126
| 238 void executeInsts(); 239
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| 240 /** Writebacks instructions. In our model, the instruction's execute() 241 * function atomically reads registers, executes, and writes registers. 242 * Thus this writeback only wakes up dependent instructions, and informs 243 * the scoreboard of registers becoming ready. 244 */ 245 void writebackInsts(); 246 247 /** Returns the number of valid, non-squashed instructions coming from 248 * rename to dispatch. 249 */ 250 unsigned validInstsFromRename(); 251 252 /** Reads the stall signals. */ 253 void readStallSignals(unsigned tid); 254 255 /** Checks if any of the stall conditions are currently true. */ 256 bool checkStall(unsigned tid); 257 258 /** Processes inputs and changes state accordingly. */ 259 void checkSignalsAndUpdate(unsigned tid); 260 261 /** Sorts instructions coming from rename into lists separated by thread. */ 262 void sortInsts(); 263
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127 public:
| 264 public:
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| 265 /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and 266 * Writeback to run for one cycle. 267 */
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128 void tick(); 129
| 268 void tick(); 269
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130 void iew();
| 270 private: 271 void updateExeInstStats(DynInstPtr &inst);
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131
| 272
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132 //Interfaces to objects inside and outside of IEW. 133 /** Time buffer interface. */
| 273 /** Pointer to main time buffer used for backwards communication. */
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134 TimeBuffer<TimeStruct> *timeBuffer; 135
| 274 TimeBuffer<TimeStruct> *timeBuffer; 275
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| 276 /** Wire to write information heading to previous stages. */ 277 typename TimeBuffer<TimeStruct>::wire toFetch; 278
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136 /** Wire to get commit's output from backwards time buffer. */ 137 typename TimeBuffer<TimeStruct>::wire fromCommit; 138 139 /** Wire to write information heading to previous stages. */ 140 typename TimeBuffer<TimeStruct>::wire toRename; 141 142 /** Rename instruction queue interface. */ 143 TimeBuffer<RenameStruct> *renameQueue; 144 145 /** Wire to get rename's output from rename queue. */ 146 typename TimeBuffer<RenameStruct>::wire fromRename; 147 148 /** Issue stage queue. */ 149 TimeBuffer<IssueStruct> issueToExecQueue; 150 151 /** Wire to read information from the issue stage time queue. */ 152 typename TimeBuffer<IssueStruct>::wire fromIssue; 153 154 /** 155 * IEW stage time buffer. Holds ROB indices of instructions that 156 * can be marked as completed. 157 */ 158 TimeBuffer<IEWStruct> *iewQueue; 159 160 /** Wire to write infromation heading to commit. */ 161 typename TimeBuffer<IEWStruct>::wire toCommit; 162
| 279 /** Wire to get commit's output from backwards time buffer. */ 280 typename TimeBuffer<TimeStruct>::wire fromCommit; 281 282 /** Wire to write information heading to previous stages. */ 283 typename TimeBuffer<TimeStruct>::wire toRename; 284 285 /** Rename instruction queue interface. */ 286 TimeBuffer<RenameStruct> *renameQueue; 287 288 /** Wire to get rename's output from rename queue. */ 289 typename TimeBuffer<RenameStruct>::wire fromRename; 290 291 /** Issue stage queue. */ 292 TimeBuffer<IssueStruct> issueToExecQueue; 293 294 /** Wire to read information from the issue stage time queue. */ 295 typename TimeBuffer<IssueStruct>::wire fromIssue; 296 297 /** 298 * IEW stage time buffer. Holds ROB indices of instructions that 299 * can be marked as completed. 300 */ 301 TimeBuffer<IEWStruct> *iewQueue; 302 303 /** Wire to write infromation heading to commit. */ 304 typename TimeBuffer<IEWStruct>::wire toCommit; 305
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163 //Will need internal queue to hold onto instructions coming from 164 //the rename stage in case of a stall.
| 306 /** Queue of all instructions coming from rename this cycle. */ 307 std::queue<DynInstPtr> insts[Impl::MaxThreads]; 308
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165 /** Skid buffer between rename and IEW. */
| 309 /** Skid buffer between rename and IEW. */
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166 std::queue<RenameStruct> skidBuffer;
| 310 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
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167
| 311
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168 protected:
| 312 /** Scoreboard pointer. */ 313 Scoreboard* scoreboard; 314 315 public:
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169 /** Instruction queue. */ 170 IQ instQueue; 171
| 316 /** Instruction queue. */ 317 IQ instQueue; 318
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172 LDSTQ ldstQueue;
| 319 /** Load / store queue. */ 320 LSQ ldstQueue;
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173
| 321
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174#if !FULL_SYSTEM 175 public: 176 void lsqWriteback(); 177#endif
| 322 /** Pointer to the functional unit pool. */ 323 FUPool *fuPool;
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178 179 private:
| 324 325 private:
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180 /** Pointer to rename map. Might not want this stage to directly 181 * access this though...
| 326 /** CPU pointer. */ 327 FullCPU *cpu; 328 329 /** Records if IEW has written to the time buffer this cycle, so that the 330 * CPU can deschedule itself if there is no activity.
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182 */
| 331 */
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183 RenameMap *renameMap;
| 332 bool wroteToTimeBuffer;
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184
| 333
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185 /** CPU interface. */ 186 FullCPU *cpu;
| 334 /** Source of possible stalls. */ 335 struct Stalls { 336 bool commit; 337 };
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187
| 338
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| 339 /** Stages that are telling IEW to stall. */ 340 Stalls stalls[Impl::MaxThreads]; 341 342 /** Debug function to print instructions that are issued this cycle. */ 343 void printAvailableInsts(); 344 345 public: 346 /** Records if the LSQ needs to be updated on the next cycle, so that 347 * IEW knows if there will be activity on the next cycle. 348 */ 349 bool updateLSQNextCycle; 350
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188 private:
| 351 private:
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| 352 /** Records if there is a fetch redirect on this cycle for each thread. */ 353 bool fetchRedirect[Impl::MaxThreads]; 354 355 /** Used to track if all instructions have been dispatched this cycle. 356 * If they have not, then blocking must have occurred, and the instructions 357 * would already be added to the skid buffer. 358 * @todo: Fix this hack. 359 */ 360 bool dispatchedAllInsts; 361 362 /** Records if the queues have been changed (inserted or issued insts), 363 * so that IEW knows to broadcast the updated amount of free entries. 364 */ 365 bool updatedQueues; 366
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189 /** Commit to IEW delay, in ticks. */ 190 unsigned commitToIEWDelay; 191 192 /** Rename to IEW delay, in ticks. */ 193 unsigned renameToIEWDelay; 194 195 /** 196 * Issue to execute delay, in ticks. What this actually represents is 197 * the amount of time it takes for an instruction to wake up, be 198 * scheduled, and sent to a FU for execution. 199 */ 200 unsigned issueToExecuteDelay; 201 202 /** Width of issue's read path, in instructions. The read path is both 203 * the skid buffer and the rename instruction queue. 204 * Note to self: is this really different than issueWidth? 205 */ 206 unsigned issueReadWidth; 207 208 /** Width of issue, in instructions. */ 209 unsigned issueWidth; 210 211 /** Width of execute, in instructions. Might make more sense to break 212 * down into FP vs int. 213 */ 214 unsigned executeWidth; 215
| 367 /** Commit to IEW delay, in ticks. */ 368 unsigned commitToIEWDelay; 369 370 /** Rename to IEW delay, in ticks. */ 371 unsigned renameToIEWDelay; 372 373 /** 374 * Issue to execute delay, in ticks. What this actually represents is 375 * the amount of time it takes for an instruction to wake up, be 376 * scheduled, and sent to a FU for execution. 377 */ 378 unsigned issueToExecuteDelay; 379 380 /** Width of issue's read path, in instructions. The read path is both 381 * the skid buffer and the rename instruction queue. 382 * Note to self: is this really different than issueWidth? 383 */ 384 unsigned issueReadWidth; 385 386 /** Width of issue, in instructions. */ 387 unsigned issueWidth; 388 389 /** Width of execute, in instructions. Might make more sense to break 390 * down into FP vs int. 391 */ 392 unsigned executeWidth; 393
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216 /** Number of cycles stage has been squashing. Used so that the stage 217 * knows when it can start unblocking, which is when the previous stage 218 * has received the stall signal and clears up its outputs.
| 394 /** Index into queue of instructions being written back. */ 395 unsigned wbNumInst; 396 397 /** Cycle number within the queue of instructions being written back. 398 * Used in case there are too many instructions writing back at the current 399 * cycle and writesbacks need to be scheduled for the future. See comments 400 * in instToCommit().
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219 */
| 401 */
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220 unsigned cyclesSquashing;
| 402 unsigned wbCycle;
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221
| 403
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| 404 /** Number of active threads. */ 405 unsigned numThreads; 406 407 /** Pointer to list of active threads. */ 408 std::list<unsigned> *activeThreads; 409 410 /** Maximum size of the skid buffer. */ 411 unsigned skidBufferMax; 412 413 bool switchedOut; 414 415 /** Stat for total number of idle cycles. */
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222 Stats::Scalar<> iewIdleCycles;
| 416 Stats::Scalar<> iewIdleCycles;
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| 417 /** Stat for total number of squashing cycles. */
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223 Stats::Scalar<> iewSquashCycles;
| 418 Stats::Scalar<> iewSquashCycles;
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| 419 /** Stat for total number of blocking cycles. */
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224 Stats::Scalar<> iewBlockCycles;
| 420 Stats::Scalar<> iewBlockCycles;
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| 421 /** Stat for total number of unblocking cycles. */
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225 Stats::Scalar<> iewUnblockCycles;
| 422 Stats::Scalar<> iewUnblockCycles;
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226// Stats::Scalar<> iewWBInsts;
| 423 /** Stat for total number of instructions dispatched. */
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227 Stats::Scalar<> iewDispatchedInsts;
| 424 Stats::Scalar<> iewDispatchedInsts;
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| 425 /** Stat for total number of squashed instructions dispatch skips. */
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228 Stats::Scalar<> iewDispSquashedInsts;
| 426 Stats::Scalar<> iewDispSquashedInsts;
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| 427 /** Stat for total number of dispatched load instructions. */
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229 Stats::Scalar<> iewDispLoadInsts;
| 428 Stats::Scalar<> iewDispLoadInsts;
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| 429 /** Stat for total number of dispatched store instructions. */
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230 Stats::Scalar<> iewDispStoreInsts;
| 430 Stats::Scalar<> iewDispStoreInsts;
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| 431 /** Stat for total number of dispatched non speculative instructions. */
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231 Stats::Scalar<> iewDispNonSpecInsts;
| 432 Stats::Scalar<> iewDispNonSpecInsts;
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| 433 /** Stat for number of times the IQ becomes full. */
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232 Stats::Scalar<> iewIQFullEvents;
| 434 Stats::Scalar<> iewIQFullEvents;
|
| 435 /** Stat for number of times the LSQ becomes full. */ 436 Stats::Scalar<> iewLSQFullEvents; 437 /** Stat for total number of executed instructions. */
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233 Stats::Scalar<> iewExecutedInsts;
| 438 Stats::Scalar<> iewExecutedInsts;
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234 Stats::Scalar<> iewExecLoadInsts; 235 Stats::Scalar<> iewExecStoreInsts;
| 439 /** Stat for total number of executed load instructions. */ 440 Stats::Vector<> iewExecLoadInsts; 441 /** Stat for total number of executed store instructions. */ 442// Stats::Scalar<> iewExecStoreInsts; 443 /** Stat for total number of squashed instructions skipped at execute. */
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236 Stats::Scalar<> iewExecSquashedInsts;
| 444 Stats::Scalar<> iewExecSquashedInsts;
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| 445 /** Stat for total number of memory ordering violation events. */
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237 Stats::Scalar<> memOrderViolationEvents;
| 446 Stats::Scalar<> memOrderViolationEvents;
|
| 447 /** Stat for total number of incorrect predicted taken branches. */
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238 Stats::Scalar<> predictedTakenIncorrect;
| 448 Stats::Scalar<> predictedTakenIncorrect;
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| 449 /** Stat for total number of incorrect predicted not taken branches. */ 450 Stats::Scalar<> predictedNotTakenIncorrect; 451 /** Stat for total number of mispredicted branches detected at execute. */ 452 Stats::Formula branchMispredicts; 453 454 Stats::Vector<> exeSwp; 455 Stats::Vector<> exeNop; 456 Stats::Vector<> exeRefs; 457 Stats::Vector<> exeBranches; 458 459// Stats::Vector<> issued_ops; 460/* 461 Stats::Vector<> stat_fu_busy; 462 Stats::Vector2d<> stat_fuBusy; 463 Stats::Vector<> dist_unissued; 464 Stats::Vector2d<> stat_issued_inst_type; 465*/ 466 Stats::Formula issueRate; 467 Stats::Formula iewExecStoreInsts; 468// Stats::Formula issue_op_rate; 469// Stats::Formula fu_busy_rate; 470 471 Stats::Vector<> iewInstsToCommit; 472 Stats::Vector<> writebackCount; 473 Stats::Vector<> producerInst; 474 Stats::Vector<> consumerInst; 475 Stats::Vector<> wbPenalized; 476 477 Stats::Formula wbRate; 478 Stats::Formula wbFanout; 479 Stats::Formula wbPenalizedRate;
|
239}; 240
| 480}; 481
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241#endif // __CPU_O3_CPU_IEW_HH__
| 482#endif // __CPU_O3_IEW_HH__
|
| |