1/*
| 1/*
|
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
| 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
|
3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
| 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
| 27 * 28 * Authors: Kevin Lim
|
27 */ 28
| 29 */ 30
|
29#ifndef __CPU_O3_IEW_HH__ 30#define __CPU_O3_IEW_HH__
| 31//Todo: Update with statuses. 32//Need to handle delaying writes to the writeback bus if it's full at the 33//given time.
|
31
| 34
|
| 35#ifndef __CPU_O3_CPU_SIMPLE_IEW_HH__ 36#define __CPU_O3_CPU_SIMPLE_IEW_HH__ 37
|
32#include <queue> 33
| 38#include <queue> 39
|
| 40#include "config/full_system.hh"
|
34#include "base/statistics.hh" 35#include "base/timebuf.hh"
| 41#include "base/statistics.hh" 42#include "base/timebuf.hh"
|
36#include "config/full_system.hh"
| |
37#include "cpu/o3/comm.hh"
| 43#include "cpu/o3/comm.hh"
|
38#include "cpu/o3/scoreboard.hh" 39#include "cpu/o3/lsq.hh"
| |
40
| 44
|
41class FUPool; 42 43/** 44 * DefaultIEW handles both single threaded and SMT IEW 45 * (issue/execute/writeback). It handles the dispatching of 46 * instructions to the LSQ/IQ as part of the issue stage, and has the 47 * IQ try to issue instructions each cycle. The execute latency is 48 * actually tied into the issue latency to allow the IQ to be able to 49 * do back-to-back scheduling without having to speculatively schedule 50 * instructions. This happens by having the IQ have access to the 51 * functional units, and the IQ gets the execution latencies from the 52 * FUs when it issues instructions. Instructions reach the execute 53 * stage on the last cycle of their execution, which is when the IQ 54 * knows to wake up any dependent instructions, allowing back to back 55 * scheduling. The execute portion of IEW separates memory 56 * instructions from non-memory instructions, either telling the LSQ 57 * to execute the instruction, or executing the instruction directly. 58 * The writeback portion of IEW completes the instructions by waking 59 * up any dependents, and marking the register ready on the 60 * scoreboard. 61 */
| |
62template<class Impl>
| 45template<class Impl>
|
63class DefaultIEW
| 46class SimpleIEW
|
64{ 65 private: 66 //Typedefs from Impl 67 typedef typename Impl::CPUPol CPUPol; 68 typedef typename Impl::DynInstPtr DynInstPtr; 69 typedef typename Impl::FullCPU FullCPU; 70 typedef typename Impl::Params Params; 71 72 typedef typename CPUPol::IQ IQ; 73 typedef typename CPUPol::RenameMap RenameMap;
| 47{ 48 private: 49 //Typedefs from Impl 50 typedef typename Impl::CPUPol CPUPol; 51 typedef typename Impl::DynInstPtr DynInstPtr; 52 typedef typename Impl::FullCPU FullCPU; 53 typedef typename Impl::Params Params; 54 55 typedef typename CPUPol::IQ IQ; 56 typedef typename CPUPol::RenameMap RenameMap;
|
74 typedef typename CPUPol::LSQ LSQ;
| 57 typedef typename CPUPol::LDSTQ LDSTQ;
|
75 76 typedef typename CPUPol::TimeStruct TimeStruct; 77 typedef typename CPUPol::IEWStruct IEWStruct; 78 typedef typename CPUPol::RenameStruct RenameStruct; 79 typedef typename CPUPol::IssueStruct IssueStruct; 80 81 friend class Impl::FullCPU;
| 58 59 typedef typename CPUPol::TimeStruct TimeStruct; 60 typedef typename CPUPol::IEWStruct IEWStruct; 61 typedef typename CPUPol::RenameStruct RenameStruct; 62 typedef typename CPUPol::IssueStruct IssueStruct; 63 64 friend class Impl::FullCPU;
|
82 friend class CPUPol::IQ; 83
| |
84 public:
| 65 public:
|
85 /** Overall IEW stage status. Used to determine if the CPU can 86 * deschedule itself due to a lack of activity. 87 */
| |
88 enum Status {
| 66 enum Status {
|
89 Active, 90 Inactive 91 }; 92 93 /** Status for Issue, Execute, and Writeback stages. */ 94 enum StageStatus {
| |
95 Running, 96 Blocked, 97 Idle,
| 67 Running, 68 Blocked, 69 Idle,
|
98 StartSquash,
| |
99 Squashing, 100 Unblocking 101 }; 102 103 private:
| 70 Squashing, 71 Unblocking 72 }; 73 74 private:
|
104 /** Overall stage status. */
| |
105 Status _status;
| 75 Status _status;
|
106 /** Dispatch status. */ 107 StageStatus dispatchStatus[Impl::MaxThreads]; 108 /** Execute status. */ 109 StageStatus exeStatus; 110 /** Writeback status. */ 111 StageStatus wbStatus;
| 76 Status _issueStatus; 77 Status _exeStatus; 78 Status _wbStatus;
|
112 113 public:
| 79 80 public:
|
114 /** LdWriteback event for a load completion. */ 115 class LdWritebackEvent : public Event {
| 81 class WritebackEvent : public Event {
|
116 private:
| 82 private:
|
117 /** Instruction that is writing back data to the register file. */
| |
118 DynInstPtr inst;
| 83 DynInstPtr inst;
|
119 /** Pointer to IEW stage. */ 120 DefaultIEW<Impl> *iewStage;
| 84 SimpleIEW<Impl> *iewStage;
|
121 122 public:
| 85 86 public:
|
123 /** Constructs a load writeback event. */ 124 LdWritebackEvent(DynInstPtr &_inst, DefaultIEW<Impl> *_iew);
| 87 WritebackEvent(DynInstPtr &_inst, SimpleIEW<Impl> *_iew);
|
125
| 88
|
126 /** Processes writeback event. */
| |
127 virtual void process();
| 89 virtual void process();
|
128 /** Returns the description of the writeback event. */
| |
129 virtual const char *description(); 130 }; 131 132 public:
| 90 virtual const char *description(); 91 }; 92 93 public:
|
133 /** Constructs a DefaultIEW with the given parameters. */ 134 DefaultIEW(Params *params);
| 94 SimpleIEW(Params ¶ms);
|
135
| 95
|
136 /** Returns the name of the DefaultIEW stage. */ 137 std::string name() const; 138 139 /** Registers statistics. */
| |
140 void regStats(); 141
| 96 void regStats(); 97
|
142 /** Initializes stage; sends back the number of free IQ and LSQ entries. */ 143 void initStage(); 144 145 /** Sets CPU pointer for IEW, IQ, and LSQ. */
| |
146 void setCPU(FullCPU *cpu_ptr); 147
| 98 void setCPU(FullCPU *cpu_ptr); 99
|
148 /** Sets main time buffer used for backwards communication. */
| |
149 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 150
| 100 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 101
|
151 /** Sets time buffer for getting instructions coming from rename. */
| |
152 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 153
| 102 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 103
|
154 /** Sets time buffer to pass on instructions to commit. */
| |
155 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 156
| 104 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 105
|
157 /** Sets pointer to list of active threads. */ 158 void setActiveThreads(std::list<unsigned> *at_ptr);
| 106 void setRenameMap(RenameMap *rm_ptr);
|
159
| 107
|
160 /** Sets pointer to the scoreboard. */ 161 void setScoreboard(Scoreboard *sb_ptr);
| 108 void squash();
|
162
| 109
|
163 void switchOut();
| 110 void squashDueToBranch(DynInstPtr &inst);
|
164
| 111
|
165 void doSwitchOut();
| 112 void squashDueToMem(DynInstPtr &inst);
|
166
| 113
|
167 void takeOverFrom();
| 114 void block();
|
168
| 115
|
169 bool isSwitchedOut() { return switchedOut; }
| 116 inline void unblock();
|
170
| 117
|
171 /** Sets page table pointer within LSQ. */ 172// void setPageTable(PageTable *pt_ptr); 173 174 /** Squashes instructions in IEW for a specific thread. */ 175 void squash(unsigned tid); 176 177 /** Wakes all dependents of a completed instruction. */
| |
178 void wakeDependents(DynInstPtr &inst); 179
| 118 void wakeDependents(DynInstPtr &inst); 119
|
180 /** Tells memory dependence unit that a memory instruction needs to be 181 * rescheduled. It will re-execute once replayMemInst() is called. 182 */ 183 void rescheduleMemInst(DynInstPtr &inst); 184 185 /** Re-executes all rescheduled memory instructions. */ 186 void replayMemInst(DynInstPtr &inst); 187 188 /** Sends an instruction to commit through the time buffer. */
| |
189 void instToCommit(DynInstPtr &inst); 190
| 120 void instToCommit(DynInstPtr &inst); 121
|
191 /** Inserts unused instructions of a thread into the skid buffer. */ 192 void skidInsert(unsigned tid); 193 194 /** Returns the max of the number of entries in all of the skid buffers. */ 195 int skidCount(); 196 197 /** Returns if all of the skid buffers are empty. */ 198 bool skidsEmpty(); 199 200 /** Updates overall IEW status based on all of the stages' statuses. */ 201 void updateStatus(); 202 203 /** Resets entries of the IQ and the LSQ. */ 204 void resetEntries(); 205 206 /** Tells the CPU to wakeup if it has descheduled itself due to no 207 * activity. Used mainly by the LdWritebackEvent. 208 */ 209 void wakeCPU(); 210 211 /** Reports to the CPU that there is activity this cycle. */ 212 void activityThisCycle(); 213 214 /** Tells CPU that the IEW stage is active and running. */ 215 inline void activateStage(); 216 217 /** Tells CPU that the IEW stage is inactive and idle. */ 218 inline void deactivateStage(); 219 220 /** Returns if the LSQ has any stores to writeback. */ 221 bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); } 222
| |
223 private:
| 122 private:
|
224 /** Sends commit proper information for a squash due to a branch 225 * mispredict. 226 */ 227 void squashDueToBranch(DynInstPtr &inst, unsigned thread_id);
| 123 void dispatchInsts();
|
228
| 124
|
229 /** Sends commit proper information for a squash due to a memory order 230 * violation. 231 */ 232 void squashDueToMemOrder(DynInstPtr &inst, unsigned thread_id); 233 234 /** Sends commit proper information for a squash due to memory becoming 235 * blocked (younger issued instructions must be retried). 236 */ 237 void squashDueToMemBlocked(DynInstPtr &inst, unsigned thread_id); 238 239 /** Sets Dispatch to blocked, and signals back to other stages to block. */ 240 void block(unsigned thread_id); 241 242 /** Unblocks Dispatch if the skid buffer is empty, and signals back to 243 * other stages to unblock. 244 */ 245 void unblock(unsigned thread_id); 246 247 /** Determines proper actions to take given Dispatch's status. */ 248 void dispatch(unsigned tid); 249 250 /** Dispatches instructions to IQ and LSQ. */ 251 void dispatchInsts(unsigned tid); 252 253 /** Executes instructions. In the case of memory operations, it informs the 254 * LSQ to execute the instructions. Also handles any redirects that occur 255 * due to the executed instructions. 256 */
| |
257 void executeInsts(); 258
| 125 void executeInsts(); 126
|
259 /** Writebacks instructions. In our model, the instruction's execute() 260 * function atomically reads registers, executes, and writes registers. 261 * Thus this writeback only wakes up dependent instructions, and informs 262 * the scoreboard of registers becoming ready. 263 */ 264 void writebackInsts(); 265 266 /** Returns the number of valid, non-squashed instructions coming from 267 * rename to dispatch. 268 */ 269 unsigned validInstsFromRename(); 270 271 /** Reads the stall signals. */ 272 void readStallSignals(unsigned tid); 273 274 /** Checks if any of the stall conditions are currently true. */ 275 bool checkStall(unsigned tid); 276 277 /** Processes inputs and changes state accordingly. */ 278 void checkSignalsAndUpdate(unsigned tid); 279 280 /** Sorts instructions coming from rename into lists separated by thread. */ 281 void sortInsts(); 282
| |
283 public:
| 127 public:
|
284 /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and 285 * Writeback to run for one cycle. 286 */
| |
287 void tick(); 288
| 128 void tick(); 129
|
289 private: 290 void updateExeInstStats(DynInstPtr &inst);
| 130 void iew();
|
291
| 131
|
292 /** Pointer to main time buffer used for backwards communication. */
| 132 //Interfaces to objects inside and outside of IEW. 133 /** Time buffer interface. */
|
293 TimeBuffer<TimeStruct> *timeBuffer; 294
| 134 TimeBuffer<TimeStruct> *timeBuffer; 135
|
295 /** Wire to write information heading to previous stages. */ 296 typename TimeBuffer<TimeStruct>::wire toFetch; 297
| |
298 /** Wire to get commit's output from backwards time buffer. */ 299 typename TimeBuffer<TimeStruct>::wire fromCommit; 300 301 /** Wire to write information heading to previous stages. */ 302 typename TimeBuffer<TimeStruct>::wire toRename; 303 304 /** Rename instruction queue interface. */ 305 TimeBuffer<RenameStruct> *renameQueue; 306 307 /** Wire to get rename's output from rename queue. */ 308 typename TimeBuffer<RenameStruct>::wire fromRename; 309 310 /** Issue stage queue. */ 311 TimeBuffer<IssueStruct> issueToExecQueue; 312 313 /** Wire to read information from the issue stage time queue. */ 314 typename TimeBuffer<IssueStruct>::wire fromIssue; 315 316 /** 317 * IEW stage time buffer. Holds ROB indices of instructions that 318 * can be marked as completed. 319 */ 320 TimeBuffer<IEWStruct> *iewQueue; 321 322 /** Wire to write infromation heading to commit. */ 323 typename TimeBuffer<IEWStruct>::wire toCommit; 324
| 136 /** Wire to get commit's output from backwards time buffer. */ 137 typename TimeBuffer<TimeStruct>::wire fromCommit; 138 139 /** Wire to write information heading to previous stages. */ 140 typename TimeBuffer<TimeStruct>::wire toRename; 141 142 /** Rename instruction queue interface. */ 143 TimeBuffer<RenameStruct> *renameQueue; 144 145 /** Wire to get rename's output from rename queue. */ 146 typename TimeBuffer<RenameStruct>::wire fromRename; 147 148 /** Issue stage queue. */ 149 TimeBuffer<IssueStruct> issueToExecQueue; 150 151 /** Wire to read information from the issue stage time queue. */ 152 typename TimeBuffer<IssueStruct>::wire fromIssue; 153 154 /** 155 * IEW stage time buffer. Holds ROB indices of instructions that 156 * can be marked as completed. 157 */ 158 TimeBuffer<IEWStruct> *iewQueue; 159 160 /** Wire to write infromation heading to commit. */ 161 typename TimeBuffer<IEWStruct>::wire toCommit; 162
|
325 /** Queue of all instructions coming from rename this cycle. */ 326 std::queue<DynInstPtr> insts[Impl::MaxThreads]; 327
| 163 //Will need internal queue to hold onto instructions coming from 164 //the rename stage in case of a stall.
|
328 /** Skid buffer between rename and IEW. */
| 165 /** Skid buffer between rename and IEW. */
|
329 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
| 166 std::queue<RenameStruct> skidBuffer;
|
330
| 167
|
331 /** Scoreboard pointer. */ 332 Scoreboard* scoreboard; 333 334 public:
| 168 protected:
|
335 /** Instruction queue. */ 336 IQ instQueue; 337
| 169 /** Instruction queue. */ 170 IQ instQueue; 171
|
338 /** Load / store queue. */ 339 LSQ ldstQueue;
| 172 LDSTQ ldstQueue;
|
340
| 173
|
341 /** Pointer to the functional unit pool. */ 342 FUPool *fuPool; 343 344 private: 345 /** CPU pointer. */ 346 FullCPU *cpu; 347 348 /** Records if IEW has written to the time buffer this cycle, so that the 349 * CPU can deschedule itself if there is no activity. 350 */ 351 bool wroteToTimeBuffer; 352 353 /** Source of possible stalls. */ 354 struct Stalls { 355 bool commit; 356 }; 357 358 /** Stages that are telling IEW to stall. */ 359 Stalls stalls[Impl::MaxThreads]; 360 361 /** Debug function to print instructions that are issued this cycle. */ 362 void printAvailableInsts(); 363
| 174#if !FULL_SYSTEM
|
364 public:
| 175 public:
|
365 /** Records if the LSQ needs to be updated on the next cycle, so that 366 * IEW knows if there will be activity on the next cycle. 367 */ 368 bool updateLSQNextCycle;
| 176 void lsqWriteback(); 177#endif
|
369 370 private:
| 178 179 private:
|
371 /** Records if there is a fetch redirect on this cycle for each thread. */ 372 bool fetchRedirect[Impl::MaxThreads]; 373 374 /** Used to track if all instructions have been dispatched this cycle. 375 * If they have not, then blocking must have occurred, and the instructions 376 * would already be added to the skid buffer. 377 * @todo: Fix this hack.
| 180 /** Pointer to rename map. Might not want this stage to directly 181 * access this though...
|
378 */
| 182 */
|
379 bool dispatchedAllInsts;
| 183 RenameMap *renameMap;
|
380
| 184
|
381 /** Records if the queues have been changed (inserted or issued insts), 382 * so that IEW knows to broadcast the updated amount of free entries. 383 */ 384 bool updatedQueues;
| 185 /** CPU interface. */ 186 FullCPU *cpu;
|
385
| 187
|
| 188 private:
|
386 /** Commit to IEW delay, in ticks. */ 387 unsigned commitToIEWDelay; 388 389 /** Rename to IEW delay, in ticks. */ 390 unsigned renameToIEWDelay; 391 392 /** 393 * Issue to execute delay, in ticks. What this actually represents is 394 * the amount of time it takes for an instruction to wake up, be 395 * scheduled, and sent to a FU for execution. 396 */ 397 unsigned issueToExecuteDelay; 398 399 /** Width of issue's read path, in instructions. The read path is both 400 * the skid buffer and the rename instruction queue. 401 * Note to self: is this really different than issueWidth? 402 */ 403 unsigned issueReadWidth; 404 405 /** Width of issue, in instructions. */ 406 unsigned issueWidth; 407 408 /** Width of execute, in instructions. Might make more sense to break 409 * down into FP vs int. 410 */ 411 unsigned executeWidth; 412
| 189 /** Commit to IEW delay, in ticks. */ 190 unsigned commitToIEWDelay; 191 192 /** Rename to IEW delay, in ticks. */ 193 unsigned renameToIEWDelay; 194 195 /** 196 * Issue to execute delay, in ticks. What this actually represents is 197 * the amount of time it takes for an instruction to wake up, be 198 * scheduled, and sent to a FU for execution. 199 */ 200 unsigned issueToExecuteDelay; 201 202 /** Width of issue's read path, in instructions. The read path is both 203 * the skid buffer and the rename instruction queue. 204 * Note to self: is this really different than issueWidth? 205 */ 206 unsigned issueReadWidth; 207 208 /** Width of issue, in instructions. */ 209 unsigned issueWidth; 210 211 /** Width of execute, in instructions. Might make more sense to break 212 * down into FP vs int. 213 */ 214 unsigned executeWidth; 215
|
413 /** Index into queue of instructions being written back. */ 414 unsigned wbNumInst; 415 416 /** Cycle number within the queue of instructions being written back. 417 * Used in case there are too many instructions writing back at the current 418 * cycle and writesbacks need to be scheduled for the future. See comments 419 * in instToCommit().
| 216 /** Number of cycles stage has been squashing. Used so that the stage 217 * knows when it can start unblocking, which is when the previous stage 218 * has received the stall signal and clears up its outputs.
|
420 */
| 219 */
|
421 unsigned wbCycle;
| 220 unsigned cyclesSquashing;
|
422
| 221
|
423 /** Number of active threads. */ 424 unsigned numThreads; 425 426 /** Pointer to list of active threads. */ 427 std::list<unsigned> *activeThreads; 428 429 /** Maximum size of the skid buffer. */ 430 unsigned skidBufferMax; 431 432 bool switchedOut; 433 434 /** Stat for total number of idle cycles. */
| |
435 Stats::Scalar<> iewIdleCycles;
| 222 Stats::Scalar<> iewIdleCycles;
|
436 /** Stat for total number of squashing cycles. */
| |
437 Stats::Scalar<> iewSquashCycles;
| 223 Stats::Scalar<> iewSquashCycles;
|
438 /** Stat for total number of blocking cycles. */
| |
439 Stats::Scalar<> iewBlockCycles;
| 224 Stats::Scalar<> iewBlockCycles;
|
440 /** Stat for total number of unblocking cycles. */
| |
441 Stats::Scalar<> iewUnblockCycles;
| 225 Stats::Scalar<> iewUnblockCycles;
|
442 /** Stat for total number of instructions dispatched. */
| 226// Stats::Scalar<> iewWBInsts;
|
443 Stats::Scalar<> iewDispatchedInsts;
| 227 Stats::Scalar<> iewDispatchedInsts;
|
444 /** Stat for total number of squashed instructions dispatch skips. */
| |
445 Stats::Scalar<> iewDispSquashedInsts;
| 228 Stats::Scalar<> iewDispSquashedInsts;
|
446 /** Stat for total number of dispatched load instructions. */
| |
447 Stats::Scalar<> iewDispLoadInsts;
| 229 Stats::Scalar<> iewDispLoadInsts;
|
448 /** Stat for total number of dispatched store instructions. */
| |
449 Stats::Scalar<> iewDispStoreInsts;
| 230 Stats::Scalar<> iewDispStoreInsts;
|
450 /** Stat for total number of dispatched non speculative instructions. */
| |
451 Stats::Scalar<> iewDispNonSpecInsts;
| 231 Stats::Scalar<> iewDispNonSpecInsts;
|
452 /** Stat for number of times the IQ becomes full. */
| |
453 Stats::Scalar<> iewIQFullEvents;
| 232 Stats::Scalar<> iewIQFullEvents;
|
454 /** Stat for number of times the LSQ becomes full. */ 455 Stats::Scalar<> iewLSQFullEvents; 456 /** Stat for total number of executed instructions. */
| |
457 Stats::Scalar<> iewExecutedInsts;
| 233 Stats::Scalar<> iewExecutedInsts;
|
458 /** Stat for total number of executed load instructions. */ 459 Stats::Vector<> iewExecLoadInsts; 460 /** Stat for total number of executed store instructions. */ 461// Stats::Scalar<> iewExecStoreInsts; 462 /** Stat for total number of squashed instructions skipped at execute. */
| 234 Stats::Scalar<> iewExecLoadInsts; 235 Stats::Scalar<> iewExecStoreInsts;
|
463 Stats::Scalar<> iewExecSquashedInsts;
| 236 Stats::Scalar<> iewExecSquashedInsts;
|
464 /** Stat for total number of memory ordering violation events. */
| |
465 Stats::Scalar<> memOrderViolationEvents;
| 237 Stats::Scalar<> memOrderViolationEvents;
|
466 /** Stat for total number of incorrect predicted taken branches. */
| |
467 Stats::Scalar<> predictedTakenIncorrect;
| 238 Stats::Scalar<> predictedTakenIncorrect;
|
468 /** Stat for total number of incorrect predicted not taken branches. */ 469 Stats::Scalar<> predictedNotTakenIncorrect; 470 /** Stat for total number of mispredicted branches detected at execute. */ 471 Stats::Formula branchMispredicts; 472 473 Stats::Vector<> exeSwp; 474 Stats::Vector<> exeNop; 475 Stats::Vector<> exeRefs; 476 Stats::Vector<> exeBranches; 477 478// Stats::Vector<> issued_ops; 479/* 480 Stats::Vector<> stat_fu_busy; 481 Stats::Vector2d<> stat_fuBusy; 482 Stats::Vector<> dist_unissued; 483 Stats::Vector2d<> stat_issued_inst_type; 484*/ 485 Stats::Formula issueRate; 486 Stats::Formula iewExecStoreInsts; 487// Stats::Formula issue_op_rate; 488// Stats::Formula fu_busy_rate; 489 490 Stats::Vector<> iewInstsToCommit; 491 Stats::Vector<> writebackCount; 492 Stats::Vector<> producerInst; 493 Stats::Vector<> consumerInst; 494 Stats::Vector<> wbPenalized; 495 496 Stats::Formula wbRate; 497 Stats::Formula wbFanout; 498 Stats::Formula wbPenalizedRate;
| |
499}; 500
| 239}; 240
|
501#endif // __CPU_O3_IEW_HH__
| 241#endif // __CPU_O3_CPU_IEW_HH__
|
| |