iew.hh (10023:91faf6649de0) iew.hh (10327:5b6279635c49)
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_O3_IEW_HH__
44#define __CPU_O3_IEW_HH__
45
46#include <queue>
47#include <set>
48
49#include "base/statistics.hh"
50#include "cpu/o3/comm.hh"
51#include "cpu/o3/lsq.hh"
52#include "cpu/o3/scoreboard.hh"
53#include "cpu/timebuf.hh"
54#include "debug/IEW.hh"
55#include "sim/probe/probe.hh"
56
57struct DerivO3CPUParams;
58class FUPool;
59
60/**
61 * DefaultIEW handles both single threaded and SMT IEW
62 * (issue/execute/writeback). It handles the dispatching of
63 * instructions to the LSQ/IQ as part of the issue stage, and has the
64 * IQ try to issue instructions each cycle. The execute latency is
65 * actually tied into the issue latency to allow the IQ to be able to
66 * do back-to-back scheduling without having to speculatively schedule
67 * instructions. This happens by having the IQ have access to the
68 * functional units, and the IQ gets the execution latencies from the
69 * FUs when it issues instructions. Instructions reach the execute
70 * stage on the last cycle of their execution, which is when the IQ
71 * knows to wake up any dependent instructions, allowing back to back
72 * scheduling. The execute portion of IEW separates memory
73 * instructions from non-memory instructions, either telling the LSQ
74 * to execute the instruction, or executing the instruction directly.
75 * The writeback portion of IEW completes the instructions by waking
76 * up any dependents, and marking the register ready on the
77 * scoreboard.
78 */
79template<class Impl>
80class DefaultIEW
81{
82 private:
83 //Typedefs from Impl
84 typedef typename Impl::CPUPol CPUPol;
85 typedef typename Impl::DynInstPtr DynInstPtr;
86 typedef typename Impl::O3CPU O3CPU;
87
88 typedef typename CPUPol::IQ IQ;
89 typedef typename CPUPol::RenameMap RenameMap;
90 typedef typename CPUPol::LSQ LSQ;
91
92 typedef typename CPUPol::TimeStruct TimeStruct;
93 typedef typename CPUPol::IEWStruct IEWStruct;
94 typedef typename CPUPol::RenameStruct RenameStruct;
95 typedef typename CPUPol::IssueStruct IssueStruct;
96
97 public:
98 /** Overall IEW stage status. Used to determine if the CPU can
99 * deschedule itself due to a lack of activity.
100 */
101 enum Status {
102 Active,
103 Inactive
104 };
105
106 /** Status for Issue, Execute, and Writeback stages. */
107 enum StageStatus {
108 Running,
109 Blocked,
110 Idle,
111 StartSquash,
112 Squashing,
113 Unblocking
114 };
115
116 private:
117 /** Overall stage status. */
118 Status _status;
119 /** Dispatch status. */
120 StageStatus dispatchStatus[Impl::MaxThreads];
121 /** Execute status. */
122 StageStatus exeStatus;
123 /** Writeback status. */
124 StageStatus wbStatus;
125
126 /** Probe points. */
127 ProbePointArg<DynInstPtr> *ppMispredict;
128 ProbePointArg<DynInstPtr> *ppDispatch;
129
130 public:
131 /** Constructs a DefaultIEW with the given parameters. */
132 DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params);
133
134 /** Returns the name of the DefaultIEW stage. */
135 std::string name() const;
136
137 /** Registers statistics. */
138 void regStats();
139
140 /** Registers probes. */
141 void regProbePoints();
142
143 /** Initializes stage; sends back the number of free IQ and LSQ entries. */
144 void startupStage();
145
146 /** Sets main time buffer used for backwards communication. */
147 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
148
149 /** Sets time buffer for getting instructions coming from rename. */
150 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
151
152 /** Sets time buffer to pass on instructions to commit. */
153 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
154
155 /** Sets pointer to list of active threads. */
156 void setActiveThreads(std::list<ThreadID> *at_ptr);
157
158 /** Sets pointer to the scoreboard. */
159 void setScoreboard(Scoreboard *sb_ptr);
160
161 /** Perform sanity checks after a drain. */
162 void drainSanityCheck() const;
163
164 /** Has the stage drained? */
165 bool isDrained() const;
166
167 /** Takes over from another CPU's thread. */
168 void takeOverFrom();
169
170 /** Squashes instructions in IEW for a specific thread. */
171 void squash(ThreadID tid);
172
173 /** Wakes all dependents of a completed instruction. */
174 void wakeDependents(DynInstPtr &inst);
175
176 /** Tells memory dependence unit that a memory instruction needs to be
177 * rescheduled. It will re-execute once replayMemInst() is called.
178 */
179 void rescheduleMemInst(DynInstPtr &inst);
180
181 /** Re-executes all rescheduled memory instructions. */
182 void replayMemInst(DynInstPtr &inst);
183
184 /** Sends an instruction to commit through the time buffer. */
185 void instToCommit(DynInstPtr &inst);
186
187 /** Inserts unused instructions of a thread into the skid buffer. */
188 void skidInsert(ThreadID tid);
189
190 /** Returns the max of the number of entries in all of the skid buffers. */
191 int skidCount();
192
193 /** Returns if all of the skid buffers are empty. */
194 bool skidsEmpty();
195
196 /** Updates overall IEW status based on all of the stages' statuses. */
197 void updateStatus();
198
199 /** Resets entries of the IQ and the LSQ. */
200 void resetEntries();
201
202 /** Tells the CPU to wakeup if it has descheduled itself due to no
203 * activity. Used mainly by the LdWritebackEvent.
204 */
205 void wakeCPU();
206
207 /** Reports to the CPU that there is activity this cycle. */
208 void activityThisCycle();
209
210 /** Tells CPU that the IEW stage is active and running. */
211 inline void activateStage();
212
213 /** Tells CPU that the IEW stage is inactive and idle. */
214 inline void deactivateStage();
215
216 /** Returns if the LSQ has any stores to writeback. */
217 bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
218
219 /** Returns if the LSQ has any stores to writeback. */
220 bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); }
221
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_O3_IEW_HH__
44#define __CPU_O3_IEW_HH__
45
46#include <queue>
47#include <set>
48
49#include "base/statistics.hh"
50#include "cpu/o3/comm.hh"
51#include "cpu/o3/lsq.hh"
52#include "cpu/o3/scoreboard.hh"
53#include "cpu/timebuf.hh"
54#include "debug/IEW.hh"
55#include "sim/probe/probe.hh"
56
57struct DerivO3CPUParams;
58class FUPool;
59
60/**
61 * DefaultIEW handles both single threaded and SMT IEW
62 * (issue/execute/writeback). It handles the dispatching of
63 * instructions to the LSQ/IQ as part of the issue stage, and has the
64 * IQ try to issue instructions each cycle. The execute latency is
65 * actually tied into the issue latency to allow the IQ to be able to
66 * do back-to-back scheduling without having to speculatively schedule
67 * instructions. This happens by having the IQ have access to the
68 * functional units, and the IQ gets the execution latencies from the
69 * FUs when it issues instructions. Instructions reach the execute
70 * stage on the last cycle of their execution, which is when the IQ
71 * knows to wake up any dependent instructions, allowing back to back
72 * scheduling. The execute portion of IEW separates memory
73 * instructions from non-memory instructions, either telling the LSQ
74 * to execute the instruction, or executing the instruction directly.
75 * The writeback portion of IEW completes the instructions by waking
76 * up any dependents, and marking the register ready on the
77 * scoreboard.
78 */
79template<class Impl>
80class DefaultIEW
81{
82 private:
83 //Typedefs from Impl
84 typedef typename Impl::CPUPol CPUPol;
85 typedef typename Impl::DynInstPtr DynInstPtr;
86 typedef typename Impl::O3CPU O3CPU;
87
88 typedef typename CPUPol::IQ IQ;
89 typedef typename CPUPol::RenameMap RenameMap;
90 typedef typename CPUPol::LSQ LSQ;
91
92 typedef typename CPUPol::TimeStruct TimeStruct;
93 typedef typename CPUPol::IEWStruct IEWStruct;
94 typedef typename CPUPol::RenameStruct RenameStruct;
95 typedef typename CPUPol::IssueStruct IssueStruct;
96
97 public:
98 /** Overall IEW stage status. Used to determine if the CPU can
99 * deschedule itself due to a lack of activity.
100 */
101 enum Status {
102 Active,
103 Inactive
104 };
105
106 /** Status for Issue, Execute, and Writeback stages. */
107 enum StageStatus {
108 Running,
109 Blocked,
110 Idle,
111 StartSquash,
112 Squashing,
113 Unblocking
114 };
115
116 private:
117 /** Overall stage status. */
118 Status _status;
119 /** Dispatch status. */
120 StageStatus dispatchStatus[Impl::MaxThreads];
121 /** Execute status. */
122 StageStatus exeStatus;
123 /** Writeback status. */
124 StageStatus wbStatus;
125
126 /** Probe points. */
127 ProbePointArg<DynInstPtr> *ppMispredict;
128 ProbePointArg<DynInstPtr> *ppDispatch;
129
130 public:
131 /** Constructs a DefaultIEW with the given parameters. */
132 DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params);
133
134 /** Returns the name of the DefaultIEW stage. */
135 std::string name() const;
136
137 /** Registers statistics. */
138 void regStats();
139
140 /** Registers probes. */
141 void regProbePoints();
142
143 /** Initializes stage; sends back the number of free IQ and LSQ entries. */
144 void startupStage();
145
146 /** Sets main time buffer used for backwards communication. */
147 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
148
149 /** Sets time buffer for getting instructions coming from rename. */
150 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
151
152 /** Sets time buffer to pass on instructions to commit. */
153 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
154
155 /** Sets pointer to list of active threads. */
156 void setActiveThreads(std::list<ThreadID> *at_ptr);
157
158 /** Sets pointer to the scoreboard. */
159 void setScoreboard(Scoreboard *sb_ptr);
160
161 /** Perform sanity checks after a drain. */
162 void drainSanityCheck() const;
163
164 /** Has the stage drained? */
165 bool isDrained() const;
166
167 /** Takes over from another CPU's thread. */
168 void takeOverFrom();
169
170 /** Squashes instructions in IEW for a specific thread. */
171 void squash(ThreadID tid);
172
173 /** Wakes all dependents of a completed instruction. */
174 void wakeDependents(DynInstPtr &inst);
175
176 /** Tells memory dependence unit that a memory instruction needs to be
177 * rescheduled. It will re-execute once replayMemInst() is called.
178 */
179 void rescheduleMemInst(DynInstPtr &inst);
180
181 /** Re-executes all rescheduled memory instructions. */
182 void replayMemInst(DynInstPtr &inst);
183
184 /** Sends an instruction to commit through the time buffer. */
185 void instToCommit(DynInstPtr &inst);
186
187 /** Inserts unused instructions of a thread into the skid buffer. */
188 void skidInsert(ThreadID tid);
189
190 /** Returns the max of the number of entries in all of the skid buffers. */
191 int skidCount();
192
193 /** Returns if all of the skid buffers are empty. */
194 bool skidsEmpty();
195
196 /** Updates overall IEW status based on all of the stages' statuses. */
197 void updateStatus();
198
199 /** Resets entries of the IQ and the LSQ. */
200 void resetEntries();
201
202 /** Tells the CPU to wakeup if it has descheduled itself due to no
203 * activity. Used mainly by the LdWritebackEvent.
204 */
205 void wakeCPU();
206
207 /** Reports to the CPU that there is activity this cycle. */
208 void activityThisCycle();
209
210 /** Tells CPU that the IEW stage is active and running. */
211 inline void activateStage();
212
213 /** Tells CPU that the IEW stage is inactive and idle. */
214 inline void deactivateStage();
215
216 /** Returns if the LSQ has any stores to writeback. */
217 bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
218
219 /** Returns if the LSQ has any stores to writeback. */
220 bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); }
221
222 void incrWb(InstSeqNum &sn)
223 {
224 ++wbOutstanding;
225 if (wbOutstanding == wbMax)
226 ableToIssue = false;
227 DPRINTF(IEW, "wbOutstanding: %i [sn:%lli]\n", wbOutstanding, sn);
228 assert(wbOutstanding <= wbMax);
229#ifdef DEBUG
230 wbList.insert(sn);
231#endif
232 }
233
234 void decrWb(InstSeqNum &sn)
235 {
236 if (wbOutstanding == wbMax)
237 ableToIssue = true;
238 wbOutstanding--;
239 DPRINTF(IEW, "wbOutstanding: %i [sn:%lli]\n", wbOutstanding, sn);
240 assert(wbOutstanding >= 0);
241#ifdef DEBUG
242 assert(wbList.find(sn) != wbList.end());
243 wbList.erase(sn);
244#endif
245 }
246
247#ifdef DEBUG
248 std::set<InstSeqNum> wbList;
249
250 void dumpWb()
251 {
252 std::set<InstSeqNum>::iterator wb_it = wbList.begin();
253 while (wb_it != wbList.end()) {
254 cprintf("[sn:%lli]\n",
255 (*wb_it));
256 wb_it++;
257 }
258 }
259#endif
260
261 bool canIssue() { return ableToIssue; }
262
263 bool ableToIssue;
264
265 /** Check misprediction */
266 void checkMisprediction(DynInstPtr &inst);
267
268 private:
269 /** Sends commit proper information for a squash due to a branch
270 * mispredict.
271 */
272 void squashDueToBranch(DynInstPtr &inst, ThreadID tid);
273
274 /** Sends commit proper information for a squash due to a memory order
275 * violation.
276 */
277 void squashDueToMemOrder(DynInstPtr &inst, ThreadID tid);
278
279 /** Sends commit proper information for a squash due to memory becoming
280 * blocked (younger issued instructions must be retried).
281 */
282 void squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid);
283
284 /** Sets Dispatch to blocked, and signals back to other stages to block. */
285 void block(ThreadID tid);
286
287 /** Unblocks Dispatch if the skid buffer is empty, and signals back to
288 * other stages to unblock.
289 */
290 void unblock(ThreadID tid);
291
292 /** Determines proper actions to take given Dispatch's status. */
293 void dispatch(ThreadID tid);
294
295 /** Dispatches instructions to IQ and LSQ. */
296 void dispatchInsts(ThreadID tid);
297
298 /** Executes instructions. In the case of memory operations, it informs the
299 * LSQ to execute the instructions. Also handles any redirects that occur
300 * due to the executed instructions.
301 */
302 void executeInsts();
303
304 /** Writebacks instructions. In our model, the instruction's execute()
305 * function atomically reads registers, executes, and writes registers.
306 * Thus this writeback only wakes up dependent instructions, and informs
307 * the scoreboard of registers becoming ready.
308 */
309 void writebackInsts();
310
311 /** Returns the number of valid, non-squashed instructions coming from
312 * rename to dispatch.
313 */
314 unsigned validInstsFromRename();
315
316 /** Reads the stall signals. */
317 void readStallSignals(ThreadID tid);
318
319 /** Checks if any of the stall conditions are currently true. */
320 bool checkStall(ThreadID tid);
321
322 /** Processes inputs and changes state accordingly. */
323 void checkSignalsAndUpdate(ThreadID tid);
324
325 /** Removes instructions from rename from a thread's instruction list. */
326 void emptyRenameInsts(ThreadID tid);
327
328 /** Sorts instructions coming from rename into lists separated by thread. */
329 void sortInsts();
330
331 public:
332 /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and
333 * Writeback to run for one cycle.
334 */
335 void tick();
336
337 private:
338 /** Updates execution stats based on the instruction. */
339 void updateExeInstStats(DynInstPtr &inst);
340
341 /** Pointer to main time buffer used for backwards communication. */
342 TimeBuffer<TimeStruct> *timeBuffer;
343
344 /** Wire to write information heading to previous stages. */
345 typename TimeBuffer<TimeStruct>::wire toFetch;
346
347 /** Wire to get commit's output from backwards time buffer. */
348 typename TimeBuffer<TimeStruct>::wire fromCommit;
349
350 /** Wire to write information heading to previous stages. */
351 typename TimeBuffer<TimeStruct>::wire toRename;
352
353 /** Rename instruction queue interface. */
354 TimeBuffer<RenameStruct> *renameQueue;
355
356 /** Wire to get rename's output from rename queue. */
357 typename TimeBuffer<RenameStruct>::wire fromRename;
358
359 /** Issue stage queue. */
360 TimeBuffer<IssueStruct> issueToExecQueue;
361
362 /** Wire to read information from the issue stage time queue. */
363 typename TimeBuffer<IssueStruct>::wire fromIssue;
364
365 /**
366 * IEW stage time buffer. Holds ROB indices of instructions that
367 * can be marked as completed.
368 */
369 TimeBuffer<IEWStruct> *iewQueue;
370
371 /** Wire to write infromation heading to commit. */
372 typename TimeBuffer<IEWStruct>::wire toCommit;
373
374 /** Queue of all instructions coming from rename this cycle. */
375 std::queue<DynInstPtr> insts[Impl::MaxThreads];
376
377 /** Skid buffer between rename and IEW. */
378 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
379
380 /** Scoreboard pointer. */
381 Scoreboard* scoreboard;
382
383 private:
384 /** CPU pointer. */
385 O3CPU *cpu;
386
387 /** Records if IEW has written to the time buffer this cycle, so that the
388 * CPU can deschedule itself if there is no activity.
389 */
390 bool wroteToTimeBuffer;
391
392 /** Source of possible stalls. */
393 struct Stalls {
394 bool commit;
395 };
396
397 /** Stages that are telling IEW to stall. */
398 Stalls stalls[Impl::MaxThreads];
399
400 /** Debug function to print instructions that are issued this cycle. */
401 void printAvailableInsts();
402
403 public:
404 /** Instruction queue. */
405 IQ instQueue;
406
407 /** Load / store queue. */
408 LSQ ldstQueue;
409
410 /** Pointer to the functional unit pool. */
411 FUPool *fuPool;
412 /** Records if the LSQ needs to be updated on the next cycle, so that
413 * IEW knows if there will be activity on the next cycle.
414 */
415 bool updateLSQNextCycle;
416
417 private:
418 /** Records if there is a fetch redirect on this cycle for each thread. */
419 bool fetchRedirect[Impl::MaxThreads];
420
421 /** Records if the queues have been changed (inserted or issued insts),
422 * so that IEW knows to broadcast the updated amount of free entries.
423 */
424 bool updatedQueues;
425
426 /** Commit to IEW delay. */
427 Cycles commitToIEWDelay;
428
429 /** Rename to IEW delay. */
430 Cycles renameToIEWDelay;
431
432 /**
433 * Issue to execute delay. What this actually represents is
434 * the amount of time it takes for an instruction to wake up, be
435 * scheduled, and sent to a FU for execution.
436 */
437 Cycles issueToExecuteDelay;
438
439 /** Width of dispatch, in instructions. */
440 unsigned dispatchWidth;
441
442 /** Width of issue, in instructions. */
443 unsigned issueWidth;
444
445 /** Index into queue of instructions being written back. */
446 unsigned wbNumInst;
447
448 /** Cycle number within the queue of instructions being written back.
449 * Used in case there are too many instructions writing back at the current
450 * cycle and writesbacks need to be scheduled for the future. See comments
451 * in instToCommit().
452 */
453 unsigned wbCycle;
454
222 /** Check misprediction */
223 void checkMisprediction(DynInstPtr &inst);
224
225 private:
226 /** Sends commit proper information for a squash due to a branch
227 * mispredict.
228 */
229 void squashDueToBranch(DynInstPtr &inst, ThreadID tid);
230
231 /** Sends commit proper information for a squash due to a memory order
232 * violation.
233 */
234 void squashDueToMemOrder(DynInstPtr &inst, ThreadID tid);
235
236 /** Sends commit proper information for a squash due to memory becoming
237 * blocked (younger issued instructions must be retried).
238 */
239 void squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid);
240
241 /** Sets Dispatch to blocked, and signals back to other stages to block. */
242 void block(ThreadID tid);
243
244 /** Unblocks Dispatch if the skid buffer is empty, and signals back to
245 * other stages to unblock.
246 */
247 void unblock(ThreadID tid);
248
249 /** Determines proper actions to take given Dispatch's status. */
250 void dispatch(ThreadID tid);
251
252 /** Dispatches instructions to IQ and LSQ. */
253 void dispatchInsts(ThreadID tid);
254
255 /** Executes instructions. In the case of memory operations, it informs the
256 * LSQ to execute the instructions. Also handles any redirects that occur
257 * due to the executed instructions.
258 */
259 void executeInsts();
260
261 /** Writebacks instructions. In our model, the instruction's execute()
262 * function atomically reads registers, executes, and writes registers.
263 * Thus this writeback only wakes up dependent instructions, and informs
264 * the scoreboard of registers becoming ready.
265 */
266 void writebackInsts();
267
268 /** Returns the number of valid, non-squashed instructions coming from
269 * rename to dispatch.
270 */
271 unsigned validInstsFromRename();
272
273 /** Reads the stall signals. */
274 void readStallSignals(ThreadID tid);
275
276 /** Checks if any of the stall conditions are currently true. */
277 bool checkStall(ThreadID tid);
278
279 /** Processes inputs and changes state accordingly. */
280 void checkSignalsAndUpdate(ThreadID tid);
281
282 /** Removes instructions from rename from a thread's instruction list. */
283 void emptyRenameInsts(ThreadID tid);
284
285 /** Sorts instructions coming from rename into lists separated by thread. */
286 void sortInsts();
287
288 public:
289 /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and
290 * Writeback to run for one cycle.
291 */
292 void tick();
293
294 private:
295 /** Updates execution stats based on the instruction. */
296 void updateExeInstStats(DynInstPtr &inst);
297
298 /** Pointer to main time buffer used for backwards communication. */
299 TimeBuffer<TimeStruct> *timeBuffer;
300
301 /** Wire to write information heading to previous stages. */
302 typename TimeBuffer<TimeStruct>::wire toFetch;
303
304 /** Wire to get commit's output from backwards time buffer. */
305 typename TimeBuffer<TimeStruct>::wire fromCommit;
306
307 /** Wire to write information heading to previous stages. */
308 typename TimeBuffer<TimeStruct>::wire toRename;
309
310 /** Rename instruction queue interface. */
311 TimeBuffer<RenameStruct> *renameQueue;
312
313 /** Wire to get rename's output from rename queue. */
314 typename TimeBuffer<RenameStruct>::wire fromRename;
315
316 /** Issue stage queue. */
317 TimeBuffer<IssueStruct> issueToExecQueue;
318
319 /** Wire to read information from the issue stage time queue. */
320 typename TimeBuffer<IssueStruct>::wire fromIssue;
321
322 /**
323 * IEW stage time buffer. Holds ROB indices of instructions that
324 * can be marked as completed.
325 */
326 TimeBuffer<IEWStruct> *iewQueue;
327
328 /** Wire to write infromation heading to commit. */
329 typename TimeBuffer<IEWStruct>::wire toCommit;
330
331 /** Queue of all instructions coming from rename this cycle. */
332 std::queue<DynInstPtr> insts[Impl::MaxThreads];
333
334 /** Skid buffer between rename and IEW. */
335 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
336
337 /** Scoreboard pointer. */
338 Scoreboard* scoreboard;
339
340 private:
341 /** CPU pointer. */
342 O3CPU *cpu;
343
344 /** Records if IEW has written to the time buffer this cycle, so that the
345 * CPU can deschedule itself if there is no activity.
346 */
347 bool wroteToTimeBuffer;
348
349 /** Source of possible stalls. */
350 struct Stalls {
351 bool commit;
352 };
353
354 /** Stages that are telling IEW to stall. */
355 Stalls stalls[Impl::MaxThreads];
356
357 /** Debug function to print instructions that are issued this cycle. */
358 void printAvailableInsts();
359
360 public:
361 /** Instruction queue. */
362 IQ instQueue;
363
364 /** Load / store queue. */
365 LSQ ldstQueue;
366
367 /** Pointer to the functional unit pool. */
368 FUPool *fuPool;
369 /** Records if the LSQ needs to be updated on the next cycle, so that
370 * IEW knows if there will be activity on the next cycle.
371 */
372 bool updateLSQNextCycle;
373
374 private:
375 /** Records if there is a fetch redirect on this cycle for each thread. */
376 bool fetchRedirect[Impl::MaxThreads];
377
378 /** Records if the queues have been changed (inserted or issued insts),
379 * so that IEW knows to broadcast the updated amount of free entries.
380 */
381 bool updatedQueues;
382
383 /** Commit to IEW delay. */
384 Cycles commitToIEWDelay;
385
386 /** Rename to IEW delay. */
387 Cycles renameToIEWDelay;
388
389 /**
390 * Issue to execute delay. What this actually represents is
391 * the amount of time it takes for an instruction to wake up, be
392 * scheduled, and sent to a FU for execution.
393 */
394 Cycles issueToExecuteDelay;
395
396 /** Width of dispatch, in instructions. */
397 unsigned dispatchWidth;
398
399 /** Width of issue, in instructions. */
400 unsigned issueWidth;
401
402 /** Index into queue of instructions being written back. */
403 unsigned wbNumInst;
404
405 /** Cycle number within the queue of instructions being written back.
406 * Used in case there are too many instructions writing back at the current
407 * cycle and writesbacks need to be scheduled for the future. See comments
408 * in instToCommit().
409 */
410 unsigned wbCycle;
411
455 /** Number of instructions in flight that will writeback. */
456
457 /** Number of instructions in flight that will writeback. */
458 int wbOutstanding;
459
460 /** Writeback width. */
461 unsigned wbWidth;
462
412 /** Writeback width. */
413 unsigned wbWidth;
414
463 /** Writeback width * writeback depth, where writeback depth is
464 * the number of cycles of writing back instructions that can be
465 * buffered. */
466 unsigned wbMax;
467
468 /** Number of active threads. */
469 ThreadID numThreads;
470
471 /** Pointer to list of active threads. */
472 std::list<ThreadID> *activeThreads;
473
474 /** Maximum size of the skid buffer. */
475 unsigned skidBufferMax;
476
477 /** Stat for total number of idle cycles. */
478 Stats::Scalar iewIdleCycles;
479 /** Stat for total number of squashing cycles. */
480 Stats::Scalar iewSquashCycles;
481 /** Stat for total number of blocking cycles. */
482 Stats::Scalar iewBlockCycles;
483 /** Stat for total number of unblocking cycles. */
484 Stats::Scalar iewUnblockCycles;
485 /** Stat for total number of instructions dispatched. */
486 Stats::Scalar iewDispatchedInsts;
487 /** Stat for total number of squashed instructions dispatch skips. */
488 Stats::Scalar iewDispSquashedInsts;
489 /** Stat for total number of dispatched load instructions. */
490 Stats::Scalar iewDispLoadInsts;
491 /** Stat for total number of dispatched store instructions. */
492 Stats::Scalar iewDispStoreInsts;
493 /** Stat for total number of dispatched non speculative instructions. */
494 Stats::Scalar iewDispNonSpecInsts;
495 /** Stat for number of times the IQ becomes full. */
496 Stats::Scalar iewIQFullEvents;
497 /** Stat for number of times the LSQ becomes full. */
498 Stats::Scalar iewLSQFullEvents;
499 /** Stat for total number of memory ordering violation events. */
500 Stats::Scalar memOrderViolationEvents;
501 /** Stat for total number of incorrect predicted taken branches. */
502 Stats::Scalar predictedTakenIncorrect;
503 /** Stat for total number of incorrect predicted not taken branches. */
504 Stats::Scalar predictedNotTakenIncorrect;
505 /** Stat for total number of mispredicted branches detected at execute. */
506 Stats::Formula branchMispredicts;
507
508 /** Stat for total number of executed instructions. */
509 Stats::Scalar iewExecutedInsts;
510 /** Stat for total number of executed load instructions. */
511 Stats::Vector iewExecLoadInsts;
512 /** Stat for total number of executed store instructions. */
513// Stats::Scalar iewExecStoreInsts;
514 /** Stat for total number of squashed instructions skipped at execute. */
515 Stats::Scalar iewExecSquashedInsts;
516 /** Number of executed software prefetches. */
517 Stats::Vector iewExecutedSwp;
518 /** Number of executed nops. */
519 Stats::Vector iewExecutedNop;
520 /** Number of executed meomory references. */
521 Stats::Vector iewExecutedRefs;
522 /** Number of executed branches. */
523 Stats::Vector iewExecutedBranches;
524 /** Number of executed store instructions. */
525 Stats::Formula iewExecStoreInsts;
526 /** Number of instructions executed per cycle. */
527 Stats::Formula iewExecRate;
528
529 /** Number of instructions sent to commit. */
530 Stats::Vector iewInstsToCommit;
531 /** Number of instructions that writeback. */
532 Stats::Vector writebackCount;
533 /** Number of instructions that wake consumers. */
534 Stats::Vector producerInst;
535 /** Number of instructions that wake up from producers. */
536 Stats::Vector consumerInst;
537 /** Number of instructions that were delayed in writing back due
538 * to resource contention.
539 */
540 Stats::Vector wbPenalized;
541 /** Number of instructions per cycle written back. */
542 Stats::Formula wbRate;
543 /** Average number of woken instructions per writeback. */
544 Stats::Formula wbFanout;
545 /** Number of instructions per cycle delayed in writing back . */
546 Stats::Formula wbPenalizedRate;
547};
548
549#endif // __CPU_O3_IEW_HH__
415 /** Number of active threads. */
416 ThreadID numThreads;
417
418 /** Pointer to list of active threads. */
419 std::list<ThreadID> *activeThreads;
420
421 /** Maximum size of the skid buffer. */
422 unsigned skidBufferMax;
423
424 /** Stat for total number of idle cycles. */
425 Stats::Scalar iewIdleCycles;
426 /** Stat for total number of squashing cycles. */
427 Stats::Scalar iewSquashCycles;
428 /** Stat for total number of blocking cycles. */
429 Stats::Scalar iewBlockCycles;
430 /** Stat for total number of unblocking cycles. */
431 Stats::Scalar iewUnblockCycles;
432 /** Stat for total number of instructions dispatched. */
433 Stats::Scalar iewDispatchedInsts;
434 /** Stat for total number of squashed instructions dispatch skips. */
435 Stats::Scalar iewDispSquashedInsts;
436 /** Stat for total number of dispatched load instructions. */
437 Stats::Scalar iewDispLoadInsts;
438 /** Stat for total number of dispatched store instructions. */
439 Stats::Scalar iewDispStoreInsts;
440 /** Stat for total number of dispatched non speculative instructions. */
441 Stats::Scalar iewDispNonSpecInsts;
442 /** Stat for number of times the IQ becomes full. */
443 Stats::Scalar iewIQFullEvents;
444 /** Stat for number of times the LSQ becomes full. */
445 Stats::Scalar iewLSQFullEvents;
446 /** Stat for total number of memory ordering violation events. */
447 Stats::Scalar memOrderViolationEvents;
448 /** Stat for total number of incorrect predicted taken branches. */
449 Stats::Scalar predictedTakenIncorrect;
450 /** Stat for total number of incorrect predicted not taken branches. */
451 Stats::Scalar predictedNotTakenIncorrect;
452 /** Stat for total number of mispredicted branches detected at execute. */
453 Stats::Formula branchMispredicts;
454
455 /** Stat for total number of executed instructions. */
456 Stats::Scalar iewExecutedInsts;
457 /** Stat for total number of executed load instructions. */
458 Stats::Vector iewExecLoadInsts;
459 /** Stat for total number of executed store instructions. */
460// Stats::Scalar iewExecStoreInsts;
461 /** Stat for total number of squashed instructions skipped at execute. */
462 Stats::Scalar iewExecSquashedInsts;
463 /** Number of executed software prefetches. */
464 Stats::Vector iewExecutedSwp;
465 /** Number of executed nops. */
466 Stats::Vector iewExecutedNop;
467 /** Number of executed meomory references. */
468 Stats::Vector iewExecutedRefs;
469 /** Number of executed branches. */
470 Stats::Vector iewExecutedBranches;
471 /** Number of executed store instructions. */
472 Stats::Formula iewExecStoreInsts;
473 /** Number of instructions executed per cycle. */
474 Stats::Formula iewExecRate;
475
476 /** Number of instructions sent to commit. */
477 Stats::Vector iewInstsToCommit;
478 /** Number of instructions that writeback. */
479 Stats::Vector writebackCount;
480 /** Number of instructions that wake consumers. */
481 Stats::Vector producerInst;
482 /** Number of instructions that wake up from producers. */
483 Stats::Vector consumerInst;
484 /** Number of instructions that were delayed in writing back due
485 * to resource contention.
486 */
487 Stats::Vector wbPenalized;
488 /** Number of instructions per cycle written back. */
489 Stats::Formula wbRate;
490 /** Average number of woken instructions per writeback. */
491 Stats::Formula wbFanout;
492 /** Number of instructions per cycle delayed in writing back . */
493 Stats::Formula wbPenalizedRate;
494};
495
496#endif // __CPU_O3_IEW_HH__