1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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256 void readStallSignals(unsigned tid);
257
258 /** Checks if any of the stall conditions are currently true. */
259 bool checkStall(unsigned tid);
260
261 /** Processes inputs and changes state accordingly. */
262 void checkSignalsAndUpdate(unsigned tid);
263
264 /** Sorts instructions coming from rename into lists separated by thread. */
265 void sortInsts();
266
267 public:
268 /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and
269 * Writeback to run for one cycle.
270 */
271 void tick();

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385 * the skid buffer and the rename instruction queue.
386 * Note to self: is this really different than issueWidth?
387 */
388 unsigned issueReadWidth;
389
390 /** Width of issue, in instructions. */
391 unsigned issueWidth;
392
393 /** Width of execute, in instructions. Might make more sense to break
394 * down into FP vs int.
395 */
396 unsigned executeWidth;
397
398 /** Index into queue of instructions being written back. */
399 unsigned wbNumInst;
400
401 /** Cycle number within the queue of instructions being written back.
402 * Used in case there are too many instructions writing back at the current
403 * cycle and writesbacks need to be scheduled for the future. See comments
404 * in instToCommit().
405 */

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