1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the

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19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31//Todo: Update with statuses.
32//Need to handle delaying writes to the writeback bus if it's full at the
33//given time.
34
35#ifndef __CPU_O3_CPU_SIMPLE_IEW_HH__
36#define __CPU_O3_CPU_SIMPLE_IEW_HH__
37
38#include <queue>
39
40#include "config/full_system.hh"
41#include "base/statistics.hh"
42#include "base/timebuf.hh"
43#include "cpu/o3/comm.hh"
44
45template<class Impl>
46class SimpleIEW
47{
48 private:
49 //Typedefs from Impl
50 typedef typename Impl::CPUPol CPUPol;
51 typedef typename Impl::DynInstPtr DynInstPtr;
52 typedef typename Impl::FullCPU FullCPU;
53 typedef typename Impl::Params Params;
54
55 typedef typename CPUPol::IQ IQ;
56 typedef typename CPUPol::RenameMap RenameMap;
57 typedef typename CPUPol::LDSTQ LDSTQ;
58
59 typedef typename CPUPol::TimeStruct TimeStruct;
60 typedef typename CPUPol::IEWStruct IEWStruct;
61 typedef typename CPUPol::RenameStruct RenameStruct;
62 typedef typename CPUPol::IssueStruct IssueStruct;
63
64 friend class Impl::FullCPU;
65 public:
66 enum Status {
67 Running,
68 Blocked,
69 Idle,
70 Squashing,
71 Unblocking
72 };
73
74 private:
75 Status _status;
76 Status _issueStatus;
77 Status _exeStatus;
78 Status _wbStatus;
79
80 public:
81 class WritebackEvent : public Event {
82 private:
83 DynInstPtr inst;
84 SimpleIEW<Impl> *iewStage;
85
86 public:
87 WritebackEvent(DynInstPtr &_inst, SimpleIEW<Impl> *_iew);
88
89 virtual void process();
90 virtual const char *description();
91 };
92
93 public:
94 SimpleIEW(Params &params);
95
96 void regStats();
97
98 void setCPU(FullCPU *cpu_ptr);
99
100 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
101
102 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
103
104 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
105
106 void setRenameMap(RenameMap *rm_ptr);
107
108 void squash();
109
110 void squashDueToBranch(DynInstPtr &inst);
111
112 void squashDueToMem(DynInstPtr &inst);
113
114 void block();
115
116 inline void unblock();
117
118 void wakeDependents(DynInstPtr &inst);
119
120 void instToCommit(DynInstPtr &inst);
121
122 private:
123 void dispatchInsts();
124
125 void executeInsts();
126
127 public:
128 void tick();
129
130 void iew();
131
132 //Interfaces to objects inside and outside of IEW.
133 /** Time buffer interface. */
134 TimeBuffer<TimeStruct> *timeBuffer;
135
136 /** Wire to get commit's output from backwards time buffer. */
137 typename TimeBuffer<TimeStruct>::wire fromCommit;
138
139 /** Wire to write information heading to previous stages. */
140 typename TimeBuffer<TimeStruct>::wire toRename;
141
142 /** Rename instruction queue interface. */
143 TimeBuffer<RenameStruct> *renameQueue;

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155 * IEW stage time buffer. Holds ROB indices of instructions that
156 * can be marked as completed.
157 */
158 TimeBuffer<IEWStruct> *iewQueue;
159
160 /** Wire to write infromation heading to commit. */
161 typename TimeBuffer<IEWStruct>::wire toCommit;
162
163 //Will need internal queue to hold onto instructions coming from
164 //the rename stage in case of a stall.
165 /** Skid buffer between rename and IEW. */
166 std::queue<RenameStruct> skidBuffer;
167
168 protected:
169 /** Instruction queue. */
170 IQ instQueue;
171
172 LDSTQ ldstQueue;
173
174#if !FULL_SYSTEM
175 public:
176 void lsqWriteback();
177#endif
178
179 private:
180 /** Pointer to rename map. Might not want this stage to directly
181 * access this though...
182 */
183 RenameMap *renameMap;
184
185 /** CPU interface. */
186 FullCPU *cpu;
187
188 private:
189 /** Commit to IEW delay, in ticks. */
190 unsigned commitToIEWDelay;
191
192 /** Rename to IEW delay, in ticks. */
193 unsigned renameToIEWDelay;
194
195 /**
196 * Issue to execute delay, in ticks. What this actually represents is

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208 /** Width of issue, in instructions. */
209 unsigned issueWidth;
210
211 /** Width of execute, in instructions. Might make more sense to break
212 * down into FP vs int.
213 */
214 unsigned executeWidth;
215
216 /** Number of cycles stage has been squashing. Used so that the stage
217 * knows when it can start unblocking, which is when the previous stage
218 * has received the stall signal and clears up its outputs.
219 */
220 unsigned cyclesSquashing;
221
222 Stats::Scalar<> iewIdleCycles;
223 Stats::Scalar<> iewSquashCycles;
224 Stats::Scalar<> iewBlockCycles;
225 Stats::Scalar<> iewUnblockCycles;
226// Stats::Scalar<> iewWBInsts;
227 Stats::Scalar<> iewDispatchedInsts;
228 Stats::Scalar<> iewDispSquashedInsts;
229 Stats::Scalar<> iewDispLoadInsts;
230 Stats::Scalar<> iewDispStoreInsts;
231 Stats::Scalar<> iewDispNonSpecInsts;
232 Stats::Scalar<> iewIQFullEvents;
233 Stats::Scalar<> iewExecutedInsts;
234 Stats::Scalar<> iewExecLoadInsts;
235 Stats::Scalar<> iewExecStoreInsts;
236 Stats::Scalar<> iewExecSquashedInsts;
237 Stats::Scalar<> memOrderViolationEvents;
238 Stats::Scalar<> predictedTakenIncorrect;
239};
240
241#endif // __CPU_O3_CPU_IEW_HH__