1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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265 */
266 void writebackInsts();
267
268 /** Returns the number of valid, non-squashed instructions coming from
269 * rename to dispatch.
270 */
271 unsigned validInstsFromRename();
272
273 /** Reads the stall signals. */
274 void readStallSignals(ThreadID tid);
275
276 /** Checks if any of the stall conditions are currently true. */
277 bool checkStall(ThreadID tid);
278
279 /** Processes inputs and changes state accordingly. */
280 void checkSignalsAndUpdate(ThreadID tid);
281
282 /** Removes instructions from rename from a thread's instruction list. */
283 void emptyRenameInsts(ThreadID tid);

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341 /** CPU pointer. */
342 O3CPU *cpu;
343
344 /** Records if IEW has written to the time buffer this cycle, so that the
345 * CPU can deschedule itself if there is no activity.
346 */
347 bool wroteToTimeBuffer;
348
349 /** Source of possible stalls. */
350 struct Stalls {
351 bool commit;
352 };
353
354 /** Stages that are telling IEW to stall. */
355 Stalls stalls[Impl::MaxThreads];
356
357 /** Debug function to print instructions that are issued this cycle. */
358 void printAvailableInsts();
359
360 public:
361 /** Instruction queue. */
362 IQ instQueue;
363
364 /** Load / store queue. */

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