1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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265 */
266 void writebackInsts();
267
268 /** Returns the number of valid, non-squashed instructions coming from
269 * rename to dispatch.
270 */
271 unsigned validInstsFromRename();
272
273 /** Checks if any of the stall conditions are currently true. */
274 bool checkStall(ThreadID tid);
275
276 /** Processes inputs and changes state accordingly. */
277 void checkSignalsAndUpdate(ThreadID tid);
278
279 /** Removes instructions from rename from a thread's instruction list. */
280 void emptyRenameInsts(ThreadID tid);

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338 /** CPU pointer. */
339 O3CPU *cpu;
340
341 /** Records if IEW has written to the time buffer this cycle, so that the
342 * CPU can deschedule itself if there is no activity.
343 */
344 bool wroteToTimeBuffer;
345
346 /** Debug function to print instructions that are issued this cycle. */
347 void printAvailableInsts();
348
349 public:
350 /** Instruction queue. */
351 IQ instQueue;
352
353 /** Load / store queue. */

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