fu_pool.hh (10807:dac26eb4cb64) fu_pool.hh (10814:46b6043bd32c)
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_O3_FU_POOL_HH__
44#define __CPU_O3_FU_POOL_HH__
45
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_O3_FU_POOL_HH__
44#define __CPU_O3_FU_POOL_HH__
45
46#include <array>
46#include <bitset>
47#include <list>
48#include <string>
49#include <vector>
50
51#include "cpu/op_class.hh"
52#include "params/FUPool.hh"
53#include "sim/sim_object.hh"

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66 * them as their scheduled execution events complete. This limits units in this
67 * model to either have identical issue and op latencies, or 1 cycle issue
68 * latencies.
69 */
70class FUPool : public SimObject
71{
72 private:
73 /** Maximum op execution latencies, per op class. */
47#include <bitset>
48#include <list>
49#include <string>
50#include <vector>
51
52#include "cpu/op_class.hh"
53#include "params/FUPool.hh"
54#include "sim/sim_object.hh"

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67 * them as their scheduled execution events complete. This limits units in this
68 * model to either have identical issue and op latencies, or 1 cycle issue
69 * latencies.
70 */
71class FUPool : public SimObject
72{
73 private:
74 /** Maximum op execution latencies, per op class. */
74 Cycles maxOpLatencies[Num_OpClasses];
75 std::array<Cycles, Num_OpClasses> maxOpLatencies;
75 /** Whether op is pipelined or not. */
76 /** Whether op is pipelined or not. */
76 bool pipelined[Num_OpClasses];
77 std::array<bool, Num_OpClasses> pipelined;
77
78 /** Bitvector listing capabilities of this FU pool. */
79 std::bitset<Num_OpClasses> capabilityList;
80
81 /** Bitvector listing which FUs are busy. */
82 std::vector<bool> unitBusy;
83
84 /** List of units to be freed at the end of this cycle. */

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79 /** Bitvector listing capabilities of this FU pool. */
80 std::bitset<Num_OpClasses> capabilityList;
81
82 /** Bitvector listing which FUs are busy. */
83 std::vector<bool> unitBusy;
84
85 /** List of units to be freed at the end of this cycle. */

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