1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 58 unchanged lines hidden (view full) --- 67 * model to either have identical issue and op latencies, or 1 cycle issue 68 * latencies. 69 */ 70class FUPool : public SimObject 71{ 72 private: 73 /** Maximum op execution latencies, per op class. */ 74 Cycles maxOpLatencies[Num_OpClasses]; |
75 /** Whether op is pipelined or not. */ 76 bool pipelined[Num_OpClasses]; |
77 78 /** Bitvector listing capabilities of this FU pool. */ 79 std::bitset<Num_OpClasses> capabilityList; 80 81 /** Bitvector listing which FUs are busy. */ 82 std::vector<bool> unitBusy; 83 84 /** List of units to be freed at the end of this cycle. */ --- 70 unchanged lines hidden (view full) --- 155 void dump(); 156 157 /** Returns the operation execution latency of the given capability. */ 158 Cycles getOpLatency(OpClass capability) { 159 return maxOpLatencies[capability]; 160 } 161 162 /** Returns the issue latency of the given capability. */ |
163 bool isPipelined(OpClass capability) { 164 return pipelined[capability]; |
165 } 166 167 /** Have all the FUs drained? */ 168 bool isDrained() const; 169 170 /** Takes over from another CPU's thread. */ 171 void takeOverFrom() {}; 172}; 173 174#endif // __CPU_O3_FU_POOL_HH__ |