free_list.hh (5362:0adba9a562c9) free_list.hh (5364:66d1251b7ae6)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 160 unchanged lines hidden (view full) ---

169 freeIntRegs.push(freed_reg);
170 } else if (freed_reg < numPhysicalRegs) {
171#if THE_ISA == ALPHA_ISA
172 if (freed_reg != (TheISA::ZeroReg + numPhysicalIntRegs))
173#endif
174 freeFloatRegs.push(freed_reg);
175 }
176
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 160 unchanged lines hidden (view full) ---

169 freeIntRegs.push(freed_reg);
170 } else if (freed_reg < numPhysicalRegs) {
171#if THE_ISA == ALPHA_ISA
172 if (freed_reg != (TheISA::ZeroReg + numPhysicalIntRegs))
173#endif
174 freeFloatRegs.push(freed_reg);
175 }
176
177 //assert(freeIntRegs.size() <= numPhysicalIntRegs);
177 // These assert conditions ensure that the number of free
178 // registers are not more than the # of total Physical Registers.
179 // If this were false, it would mean that registers
180 // have been freed twice, overflowing the free register
181 // pool and potentially crashing SMT workloads.
182 // ----
183 // Comment out for now so as to not potentially break
184 // CMP and single-threaded workloads
185 // ----
186 // assert(freeIntRegs.size() <= numPhysicalIntRegs);
187 // assert(freeFloatRegs.size() <= numPhysicalFloatRegs);
178}
179
180inline void
181SimpleFreeList::addIntReg(PhysRegIndex freed_reg)
182{
183 DPRINTF(FreeList,"Freeing int register %i.\n", freed_reg);
184
185 freeIntRegs.push(freed_reg);
186}
187
188inline void
189SimpleFreeList::addFloatReg(PhysRegIndex freed_reg)
190{
191 DPRINTF(FreeList,"Freeing float register %i.\n", freed_reg);
192
193 freeFloatRegs.push(freed_reg);
194}
195
196#endif // __CPU_O3_FREE_LIST_HH__
188}
189
190inline void
191SimpleFreeList::addIntReg(PhysRegIndex freed_reg)
192{
193 DPRINTF(FreeList,"Freeing int register %i.\n", freed_reg);
194
195 freeIntRegs.push(freed_reg);
196}
197
198inline void
199SimpleFreeList::addFloatReg(PhysRegIndex freed_reg)
200{
201 DPRINTF(FreeList,"Freeing float register %i.\n", freed_reg);
202
203 freeFloatRegs.push(freed_reg);
204}
205
206#endif // __CPU_O3_FREE_LIST_HH__