| free_list.hh (12105:742d80361989) | free_list.hh (12106:7784fac1b159) |
|---|---|
| 1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 169 unchanged lines hidden (view full) --- 178 179 /** Returns the number of free cc registers. */ 180 unsigned numFreeCCRegs() const { return ccList.numFreeRegs(); } 181}; 182 183inline void 184UnifiedFreeList::addReg(PhysRegIdPtr freed_reg) 185{ | 1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 169 unchanged lines hidden (view full) --- 178 179 /** Returns the number of free cc registers. */ 180 unsigned numFreeCCRegs() const { return ccList.numFreeRegs(); } 181}; 182 183inline void 184UnifiedFreeList::addReg(PhysRegIdPtr freed_reg) 185{ |
| 186 DPRINTF(FreeList,"Freeing register %i (%s).\n", freed_reg->regIdx, 187 RegClassStrings[freed_reg->regClass]); | 186 DPRINTF(FreeList,"Freeing register %i (%s).\n", freed_reg->index(), 187 freed_reg->className()); |
| 188 //Might want to add in a check for whether or not this register is 189 //already in there. A bit vector or something similar would be useful. | 188 //Might want to add in a check for whether or not this register is 189 //already in there. A bit vector or something similar would be useful. |
| 190 switch (freed_reg->regClass) { | 190 switch (freed_reg->classValue()) { |
| 191 case IntRegClass: 192 intList.addReg(freed_reg); 193 break; 194 case FloatRegClass: 195 floatList.addReg(freed_reg); 196 break; 197 case CCRegClass: 198 ccList.addReg(freed_reg); 199 break; 200 default: 201 panic("Unexpected RegClass (%s)", | 191 case IntRegClass: 192 intList.addReg(freed_reg); 193 break; 194 case FloatRegClass: 195 floatList.addReg(freed_reg); 196 break; 197 case CCRegClass: 198 ccList.addReg(freed_reg); 199 break; 200 default: 201 panic("Unexpected RegClass (%s)", |
| 202 RegClassStrings[freed_reg->regClass]); | 202 freed_reg->className()); |
| 203 } 204 205 // These assert conditions ensure that the number of free 206 // registers are not more than the # of total Physical Registers. 207 // If this were false, it would mean that registers 208 // have been freed twice, overflowing the free register 209 // pool and potentially crashing SMT workloads. 210 // ---- 211 // Comment out for now so as to not potentially break 212 // CMP and single-threaded workloads 213 // ---- 214 // assert(freeIntRegs.size() <= numPhysicalIntRegs); 215 // assert(freeFloatRegs.size() <= numPhysicalFloatRegs); 216} 217 218 219#endif // __CPU_O3_FREE_LIST_HH__ | 203 } 204 205 // These assert conditions ensure that the number of free 206 // registers are not more than the # of total Physical Registers. 207 // If this were false, it would mean that registers 208 // have been freed twice, overflowing the free register 209 // pool and potentially crashing SMT workloads. 210 // ---- 211 // Comment out for now so as to not potentially break 212 // CMP and single-threaded workloads 213 // ---- 214 // assert(freeIntRegs.size() <= numPhysicalIntRegs); 215 // assert(freeFloatRegs.size() <= numPhysicalFloatRegs); 216} 217 218 219#endif // __CPU_O3_FREE_LIST_HH__ |