free_list.hh (10934:5af8f40d8f2c) free_list.hh (10935:acd48ddd725f)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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104 SimpleFreeList intList;
105
106 /** The list of free floating point registers. */
107 SimpleFreeList floatList;
108
109 /** The list of free condition-code registers. */
110 SimpleFreeList ccList;
111
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 95 unchanged lines hidden (view full) ---

104 SimpleFreeList intList;
105
106 /** The list of free floating point registers. */
107 SimpleFreeList floatList;
108
109 /** The list of free condition-code registers. */
110 SimpleFreeList ccList;
111
112 /** The list of free vector registers. */
113 SimpleFreeList vectorList;
114
115 /**
116 * The register file object is used only to distinguish integer
117 * from floating-point physical register indices.
118 */
119 PhysRegFile *regFile;
120
121 /*
122 * We give UnifiedRenameMap internal access so it can get at the

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146 PhysRegIndex getIntReg() { return intList.getReg(); }
147
148 /** Gets a free fp register. */
149 PhysRegIndex getFloatReg() { return floatList.getReg(); }
150
151 /** Gets a free cc register. */
152 PhysRegIndex getCCReg() { return ccList.getReg(); }
153
112 /**
113 * The register file object is used only to distinguish integer
114 * from floating-point physical register indices.
115 */
116 PhysRegFile *regFile;
117
118 /*
119 * We give UnifiedRenameMap internal access so it can get at the

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143 PhysRegIndex getIntReg() { return intList.getReg(); }
144
145 /** Gets a free fp register. */
146 PhysRegIndex getFloatReg() { return floatList.getReg(); }
147
148 /** Gets a free cc register. */
149 PhysRegIndex getCCReg() { return ccList.getReg(); }
150
154 /** Gets a free vector register. */
155 PhysRegIndex getVectorReg() { return vectorList.getReg(); }
156
157 /** Adds a register back to the free list. */
158 void addReg(PhysRegIndex freed_reg);
159
160 /** Adds an integer register back to the free list. */
161 void addIntReg(PhysRegIndex freed_reg) { intList.addReg(freed_reg); }
162
163 /** Adds a fp register back to the free list. */
164 void addFloatReg(PhysRegIndex freed_reg) { floatList.addReg(freed_reg); }
165
166 /** Adds a cc register back to the free list. */
167 void addCCReg(PhysRegIndex freed_reg) { ccList.addReg(freed_reg); }
168
151 /** Adds a register back to the free list. */
152 void addReg(PhysRegIndex freed_reg);
153
154 /** Adds an integer register back to the free list. */
155 void addIntReg(PhysRegIndex freed_reg) { intList.addReg(freed_reg); }
156
157 /** Adds a fp register back to the free list. */
158 void addFloatReg(PhysRegIndex freed_reg) { floatList.addReg(freed_reg); }
159
160 /** Adds a cc register back to the free list. */
161 void addCCReg(PhysRegIndex freed_reg) { ccList.addReg(freed_reg); }
162
169 /** Adds a vector register back to the free list. */
170 void addVectorReg(PhysRegIndex freed_reg) { vectorList.addReg(freed_reg); }
171
172 /** Checks if there are any free integer registers. */
173 bool hasFreeIntRegs() const { return intList.hasFreeRegs(); }
174
175 /** Checks if there are any free fp registers. */
176 bool hasFreeFloatRegs() const { return floatList.hasFreeRegs(); }
177
178 /** Checks if there are any free cc registers. */
179 bool hasFreeCCRegs() const { return ccList.hasFreeRegs(); }
180
163 /** Checks if there are any free integer registers. */
164 bool hasFreeIntRegs() const { return intList.hasFreeRegs(); }
165
166 /** Checks if there are any free fp registers. */
167 bool hasFreeFloatRegs() const { return floatList.hasFreeRegs(); }
168
169 /** Checks if there are any free cc registers. */
170 bool hasFreeCCRegs() const { return ccList.hasFreeRegs(); }
171
181 /** Checks if there are any free vector registers. */
182 bool hasFreeVectorRegs() const { return vectorList.hasFreeRegs(); }
183
184 /** Returns the number of free integer registers. */
185 unsigned numFreeIntRegs() const { return intList.numFreeRegs(); }
186
187 /** Returns the number of free fp registers. */
188 unsigned numFreeFloatRegs() const { return floatList.numFreeRegs(); }
189
190 /** Returns the number of free cc registers. */
191 unsigned numFreeCCRegs() const { return ccList.numFreeRegs(); }
172 /** Returns the number of free integer registers. */
173 unsigned numFreeIntRegs() const { return intList.numFreeRegs(); }
174
175 /** Returns the number of free fp registers. */
176 unsigned numFreeFloatRegs() const { return floatList.numFreeRegs(); }
177
178 /** Returns the number of free cc registers. */
179 unsigned numFreeCCRegs() const { return ccList.numFreeRegs(); }
192
193 /** Returns the number of free vector registers. */
194 unsigned numFreeVectorRegs() const { return vectorList.numFreeRegs(); }
195};
196
197inline void
198UnifiedFreeList::addReg(PhysRegIndex freed_reg)
199{
200 DPRINTF(FreeList,"Freeing register %i.\n", freed_reg);
201 //Might want to add in a check for whether or not this register is
202 //already in there. A bit vector or something similar would be useful.
203 if (regFile->isIntPhysReg(freed_reg)) {
204 intList.addReg(freed_reg);
205 } else if (regFile->isFloatPhysReg(freed_reg)) {
206 floatList.addReg(freed_reg);
180};
181
182inline void
183UnifiedFreeList::addReg(PhysRegIndex freed_reg)
184{
185 DPRINTF(FreeList,"Freeing register %i.\n", freed_reg);
186 //Might want to add in a check for whether or not this register is
187 //already in there. A bit vector or something similar would be useful.
188 if (regFile->isIntPhysReg(freed_reg)) {
189 intList.addReg(freed_reg);
190 } else if (regFile->isFloatPhysReg(freed_reg)) {
191 floatList.addReg(freed_reg);
207 } else if (regFile->isCCPhysReg(freed_reg)) {
208 ccList.addReg(freed_reg);
209 } else {
192 } else {
210 assert(regFile->isVectorPhysReg(freed_reg));
211 vectorList.addReg(freed_reg);
193 assert(regFile->isCCPhysReg(freed_reg));
194 ccList.addReg(freed_reg);
212 }
213
214 // These assert conditions ensure that the number of free
215 // registers are not more than the # of total Physical Registers.
216 // If this were false, it would mean that registers
217 // have been freed twice, overflowing the free register
218 // pool and potentially crashing SMT workloads.
219 // ----
220 // Comment out for now so as to not potentially break
221 // CMP and single-threaded workloads
222 // ----
223 // assert(freeIntRegs.size() <= numPhysicalIntRegs);
224 // assert(freeFloatRegs.size() <= numPhysicalFloatRegs);
225}
226
227
228#endif // __CPU_O3_FREE_LIST_HH__
195 }
196
197 // These assert conditions ensure that the number of free
198 // registers are not more than the # of total Physical Registers.
199 // If this were false, it would mean that registers
200 // have been freed twice, overflowing the free register
201 // pool and potentially crashing SMT workloads.
202 // ----
203 // Comment out for now so as to not potentially break
204 // CMP and single-threaded workloads
205 // ----
206 // assert(freeIntRegs.size() <= numPhysicalIntRegs);
207 // assert(freeFloatRegs.size() <= numPhysicalFloatRegs);
208}
209
210
211#endif // __CPU_O3_FREE_LIST_HH__