fetch_impl.hh (9944:4ff1c5c6dcbc) fetch_impl.hh (9982:b2bfc23f932c)
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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80 decodeToFetchDelay(params->decodeToFetchDelay),
81 renameToFetchDelay(params->renameToFetchDelay),
82 iewToFetchDelay(params->iewToFetchDelay),
83 commitToFetchDelay(params->commitToFetchDelay),
84 fetchWidth(params->fetchWidth),
85 retryPkt(NULL),
86 retryTid(InvalidThreadID),
87 cacheBlkSize(cpu->cacheLineSize()),
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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80 decodeToFetchDelay(params->decodeToFetchDelay),
81 renameToFetchDelay(params->renameToFetchDelay),
82 iewToFetchDelay(params->iewToFetchDelay),
83 commitToFetchDelay(params->commitToFetchDelay),
84 fetchWidth(params->fetchWidth),
85 retryPkt(NULL),
86 retryTid(InvalidThreadID),
87 cacheBlkSize(cpu->cacheLineSize()),
88 cacheBlkMask(cacheBlkSize - 1),
88 fetchBufferSize(params->fetchBufferSize),
89 fetchBufferMask(fetchBufferSize - 1),
89 numThreads(params->numThreads),
90 numFetchingThreads(params->smtNumFetchingThreads),
91 finishTranslationEvent(this)
92{
93 if (numThreads > Impl::MaxThreads)
94 fatal("numThreads (%d) is larger than compiled limit (%d),\n"
95 "\tincrease MaxThreads in src/cpu/o3/impl.hh\n",
96 numThreads, static_cast<int>(Impl::MaxThreads));
97 if (fetchWidth > Impl::MaxWidth)
98 fatal("fetchWidth (%d) is larger than compiled limit (%d),\n"
99 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
100 fetchWidth, static_cast<int>(Impl::MaxWidth));
90 numThreads(params->numThreads),
91 numFetchingThreads(params->smtNumFetchingThreads),
92 finishTranslationEvent(this)
93{
94 if (numThreads > Impl::MaxThreads)
95 fatal("numThreads (%d) is larger than compiled limit (%d),\n"
96 "\tincrease MaxThreads in src/cpu/o3/impl.hh\n",
97 numThreads, static_cast<int>(Impl::MaxThreads));
98 if (fetchWidth > Impl::MaxWidth)
99 fatal("fetchWidth (%d) is larger than compiled limit (%d),\n"
100 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
101 fetchWidth, static_cast<int>(Impl::MaxWidth));
102 if (fetchBufferSize > cacheBlkSize)
103 fatal("fetch buffer size (%u bytes) is greater than the cache "
104 "block size (%u bytes)\n", fetchBufferSize, cacheBlkSize);
105 if (cacheBlkSize % fetchBufferSize)
106 fatal("cache block (%u bytes) is not a multiple of the "
107 "fetch buffer (%u bytes)\n", cacheBlkSize, fetchBufferSize);
101
102 std::string policy = params->smtFetchPolicy;
103
104 // Convert string to lowercase
105 std::transform(policy.begin(), policy.end(), policy.begin(),
106 (int(*)(int)) tolower);
107
108 // Figure out fetch policy

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126 fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
127 " RoundRobin,LSQcount,IQcount}\n");
128 }
129
130 // Get the size of an instruction.
131 instSize = sizeof(TheISA::MachInst);
132
133 for (int i = 0; i < Impl::MaxThreads; i++) {
108
109 std::string policy = params->smtFetchPolicy;
110
111 // Convert string to lowercase
112 std::transform(policy.begin(), policy.end(), policy.begin(),
113 (int(*)(int)) tolower);
114
115 // Figure out fetch policy

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133 fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
134 " RoundRobin,LSQcount,IQcount}\n");
135 }
136
137 // Get the size of an instruction.
138 instSize = sizeof(TheISA::MachInst);
139
140 for (int i = 0; i < Impl::MaxThreads; i++) {
134 decoder[i] = new TheISA::Decoder;
141 decoder[i] = NULL;
142 fetchBuffer[i] = NULL;
143 fetchBufferPC[i] = 0;
144 fetchBufferValid[i] = false;
135 }
136
137 branchPred = params->branchPred;
138
139 for (ThreadID tid = 0; tid < numThreads; tid++) {
145 }
146
147 branchPred = params->branchPred;
148
149 for (ThreadID tid = 0; tid < numThreads; tid++) {
140 // Create space to store a cache line.
141 cacheData[tid] = new uint8_t[cacheBlkSize];
142 cacheDataPC[tid] = 0;
143 cacheDataValid[tid] = false;
150 decoder[tid] = new TheISA::Decoder;
151 // Create space to buffer the cache line data,
152 // which may not hold the entire cache line.
153 fetchBuffer[tid] = new uint8_t[fetchBufferSize];
144 }
145}
146
147template <class Impl>
148std::string
149DefaultFetch<Impl>::name() const
150{
151 return cpu->name() + ".fetch";

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322{
323 numInst = 0;
324 interruptPending = false;
325 cacheBlocked = false;
326
327 priorityList.clear();
328
329 // Setup PC and nextPC with initial state.
154 }
155}
156
157template <class Impl>
158std::string
159DefaultFetch<Impl>::name() const
160{
161 return cpu->name() + ".fetch";

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332{
333 numInst = 0;
334 interruptPending = false;
335 cacheBlocked = false;
336
337 priorityList.clear();
338
339 // Setup PC and nextPC with initial state.
330 for (ThreadID tid = 0; tid < numThreads; tid++) {
340 for (ThreadID tid = 0; tid < numThreads; ++tid) {
331 fetchStatus[tid] = Running;
332 pc[tid] = cpu->pcState(tid);
333 fetchOffset[tid] = 0;
334 macroop[tid] = NULL;
335
336 delayedCommit[tid] = false;
337 memReq[tid] = NULL;
338
339 stalls[tid].decode = false;
340 stalls[tid].rename = false;
341 stalls[tid].iew = false;
342 stalls[tid].commit = false;
343 stalls[tid].drain = false;
344
341 fetchStatus[tid] = Running;
342 pc[tid] = cpu->pcState(tid);
343 fetchOffset[tid] = 0;
344 macroop[tid] = NULL;
345
346 delayedCommit[tid] = false;
347 memReq[tid] = NULL;
348
349 stalls[tid].decode = false;
350 stalls[tid].rename = false;
351 stalls[tid].iew = false;
352 stalls[tid].commit = false;
353 stalls[tid].drain = false;
354
355 fetchBufferPC[tid] = 0;
356 fetchBufferValid[tid] = false;
357
345 priorityList.push_back(tid);
346 }
347
348 wroteToTimeBuffer = false;
349 _status = Inactive;
358 priorityList.push_back(tid);
359 }
360
361 wroteToTimeBuffer = false;
362 _status = Inactive;
350
351 for (ThreadID tid = 0; tid < numThreads; tid++) {
352 cacheDataPC[tid] = 0;
353 cacheDataValid[tid] = false;
354 }
355}
356
357template<class Impl>
358void
359DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
360{
361 ThreadID tid = pkt->req->threadId();
362

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368 if (fetchStatus[tid] != IcacheWaitResponse ||
369 pkt->req != memReq[tid]) {
370 ++fetchIcacheSquashes;
371 delete pkt->req;
372 delete pkt;
373 return;
374 }
375
363}
364
365template<class Impl>
366void
367DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
368{
369 ThreadID tid = pkt->req->threadId();
370

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376 if (fetchStatus[tid] != IcacheWaitResponse ||
377 pkt->req != memReq[tid]) {
378 ++fetchIcacheSquashes;
379 delete pkt->req;
380 delete pkt;
381 return;
382 }
383
376 memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize);
377 cacheDataValid[tid] = true;
384 memcpy(fetchBuffer[tid], pkt->getPtr<uint8_t>(), fetchBufferSize);
385 fetchBufferValid[tid] = true;
378
379 // Wake up the CPU (if it went to sleep and was waiting on
380 // this completion event).
381 cpu->wakeCPU();
382
383 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
384 tid);
385

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568 // Cache is blocked, or
569 // while an interrupt is pending and we're not in PAL mode, or
570 // fetch is switched out.
571 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
572 tid);
573 return false;
574 }
575
386
387 // Wake up the CPU (if it went to sleep and was waiting on
388 // this completion event).
389 cpu->wakeCPU();
390
391 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
392 tid);
393

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576 // Cache is blocked, or
577 // while an interrupt is pending and we're not in PAL mode, or
578 // fetch is switched out.
579 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
580 tid);
581 return false;
582 }
583
576 // Align the fetch address so it's at the start of a cache block.
577 Addr block_PC = icacheBlockAlignPC(vaddr);
584 // Align the fetch address to the start of a fetch buffer segment.
585 Addr fetchBufferBlockPC = fetchBufferAlignPC(vaddr);
578
579 DPRINTF(Fetch, "[tid:%i] Fetching cache line %#x for addr %#x\n",
586
587 DPRINTF(Fetch, "[tid:%i] Fetching cache line %#x for addr %#x\n",
580 tid, block_PC, vaddr);
588 tid, fetchBufferBlockPC, vaddr);
581
582 // Setup the memReq to do a read of the first instruction's address.
583 // Set the appropriate read size and flags as well.
584 // Build request here.
585 RequestPtr mem_req =
589
590 // Setup the memReq to do a read of the first instruction's address.
591 // Set the appropriate read size and flags as well.
592 // Build request here.
593 RequestPtr mem_req =
586 new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH,
587 cpu->instMasterId(), pc, cpu->thread[tid]->contextId(), tid);
594 new Request(tid, fetchBufferBlockPC, fetchBufferSize,
595 Request::INST_FETCH, cpu->instMasterId(), pc,
596 cpu->thread[tid]->contextId(), tid);
588
589 memReq[tid] = mem_req;
590
591 // Initiate translation of the icache block
592 fetchStatus[tid] = ItlbWait;
593 FetchTranslation *trans = new FetchTranslation(this);
594 cpu->itb->translateTiming(mem_req, cpu->thread[tid]->getTC(),
595 trans, BaseTLB::Execute);
596 return true;
597}
598
599template <class Impl>
600void
601DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req)
602{
603 ThreadID tid = mem_req->threadId();
597
598 memReq[tid] = mem_req;
599
600 // Initiate translation of the icache block
601 fetchStatus[tid] = ItlbWait;
602 FetchTranslation *trans = new FetchTranslation(this);
603 cpu->itb->translateTiming(mem_req, cpu->thread[tid]->getTC(),
604 trans, BaseTLB::Execute);
605 return true;
606}
607
608template <class Impl>
609void
610DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req)
611{
612 ThreadID tid = mem_req->threadId();
604 Addr block_PC = mem_req->getVaddr();
613 Addr fetchBufferBlockPC = mem_req->getVaddr();
605
606 assert(!cpu->switchedOut());
607
608 // Wake up CPU if it was idle
609 cpu->wakeCPU();
610
611 if (fetchStatus[tid] != ItlbWait || mem_req != memReq[tid] ||
612 mem_req->getVaddr() != memReq[tid]->getVaddr()) {

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629 fetchStatus[tid] = NoGoodAddr;
630 delete mem_req;
631 memReq[tid] = NULL;
632 return;
633 }
634
635 // Build packet here.
636 PacketPtr data_pkt = new Packet(mem_req, MemCmd::ReadReq);
614
615 assert(!cpu->switchedOut());
616
617 // Wake up CPU if it was idle
618 cpu->wakeCPU();
619
620 if (fetchStatus[tid] != ItlbWait || mem_req != memReq[tid] ||
621 mem_req->getVaddr() != memReq[tid]->getVaddr()) {

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638 fetchStatus[tid] = NoGoodAddr;
639 delete mem_req;
640 memReq[tid] = NULL;
641 return;
642 }
643
644 // Build packet here.
645 PacketPtr data_pkt = new Packet(mem_req, MemCmd::ReadReq);
637 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
646 data_pkt->dataDynamicArray(new uint8_t[fetchBufferSize]);
638
647
639 cacheDataPC[tid] = block_PC;
640 cacheDataValid[tid] = false;
648 fetchBufferPC[tid] = fetchBufferBlockPC;
649 fetchBufferValid[tid] = false;
641 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
642
643 fetchedCacheLines++;
644
645 // Access the cache.
646 if (!cpu->getInstPort().sendTimingReq(data_pkt)) {
647 assert(retryPkt == NULL);
648 assert(retryTid == InvalidThreadID);

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1149 // to running, otherwise do the cache access. Possibly move this up
1150 // to tick() function.
1151 if (fetchStatus[tid] == IcacheAccessComplete) {
1152 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", tid);
1153
1154 fetchStatus[tid] = Running;
1155 status_change = true;
1156 } else if (fetchStatus[tid] == Running) {
650 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
651
652 fetchedCacheLines++;
653
654 // Access the cache.
655 if (!cpu->getInstPort().sendTimingReq(data_pkt)) {
656 assert(retryPkt == NULL);
657 assert(retryTid == InvalidThreadID);

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1158 // to running, otherwise do the cache access. Possibly move this up
1159 // to tick() function.
1160 if (fetchStatus[tid] == IcacheAccessComplete) {
1161 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", tid);
1162
1163 fetchStatus[tid] = Running;
1164 status_change = true;
1165 } else if (fetchStatus[tid] == Running) {
1157 // Align the fetch PC so its at the start of a cache block.
1158 Addr block_PC = icacheBlockAlignPC(fetchAddr);
1166 // Align the fetch PC so its at the start of a fetch buffer segment.
1167 Addr fetchBufferBlockPC = fetchBufferAlignPC(fetchAddr);
1159
1160 // If buffer is no longer valid or fetchAddr has moved to point
1161 // to the next cache block, AND we have no remaining ucode
1162 // from a macro-op, then start fetch from icache.
1168
1169 // If buffer is no longer valid or fetchAddr has moved to point
1170 // to the next cache block, AND we have no remaining ucode
1171 // from a macro-op, then start fetch from icache.
1163 if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid])
1172 if (!(fetchBufferValid[tid] && fetchBufferBlockPC == fetchBufferPC[tid])
1164 && !inRom && !macroop[tid]) {
1165 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1166 "instruction, starting at PC %s.\n", tid, thisPC);
1167
1168 fetchCacheLine(fetchAddr, tid, thisPC.instAddr());
1169
1170 if (fetchStatus[tid] == IcacheWaitResponse)
1171 ++icacheStallCycles;

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1206 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1207 "decode.\n", tid);
1208
1209 // Need to keep track of whether or not a predicted branch
1210 // ended this fetch block.
1211 bool predictedBranch = false;
1212
1213 TheISA::MachInst *cacheInsts =
1173 && !inRom && !macroop[tid]) {
1174 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1175 "instruction, starting at PC %s.\n", tid, thisPC);
1176
1177 fetchCacheLine(fetchAddr, tid, thisPC.instAddr());
1178
1179 if (fetchStatus[tid] == IcacheWaitResponse)
1180 ++icacheStallCycles;

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1215 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1216 "decode.\n", tid);
1217
1218 // Need to keep track of whether or not a predicted branch
1219 // ended this fetch block.
1220 bool predictedBranch = false;
1221
1222 TheISA::MachInst *cacheInsts =
1214 reinterpret_cast<TheISA::MachInst *>(cacheData[tid]);
1223 reinterpret_cast<TheISA::MachInst *>(fetchBuffer[tid]);
1215
1224
1216 const unsigned numInsts = cacheBlkSize / instSize;
1217 unsigned blkOffset = (fetchAddr - cacheDataPC[tid]) / instSize;
1225 const unsigned numInsts = fetchBufferSize / instSize;
1226 unsigned blkOffset = (fetchAddr - fetchBufferPC[tid]) / instSize;
1218
1219 // Loop through instruction memory from the cache.
1220 // Keep issuing while fetchWidth is available and branch is not
1221 // predicted taken
1222 while (numInst < fetchWidth && !predictedBranch) {
1223
1224 // We need to process more memory if we aren't going to get a
1225 // StaticInst from the rom, the current macroop, or what's already
1226 // in the decoder.
1227 bool needMem = !inRom && !curMacroop &&
1228 !decoder[tid]->instReady();
1229 fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
1227
1228 // Loop through instruction memory from the cache.
1229 // Keep issuing while fetchWidth is available and branch is not
1230 // predicted taken
1231 while (numInst < fetchWidth && !predictedBranch) {
1232
1233 // We need to process more memory if we aren't going to get a
1234 // StaticInst from the rom, the current macroop, or what's already
1235 // in the decoder.
1236 bool needMem = !inRom && !curMacroop &&
1237 !decoder[tid]->instReady();
1238 fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
1230 Addr block_PC = icacheBlockAlignPC(fetchAddr);
1239 Addr fetchBufferBlockPC = fetchBufferAlignPC(fetchAddr);
1231
1232 if (needMem) {
1233 // If buffer is no longer valid or fetchAddr has moved to point
1234 // to the next cache block then start fetch from icache.
1240
1241 if (needMem) {
1242 // If buffer is no longer valid or fetchAddr has moved to point
1243 // to the next cache block then start fetch from icache.
1235 if (!cacheDataValid[tid] || block_PC != cacheDataPC[tid])
1244 if (!fetchBufferValid[tid] ||
1245 fetchBufferBlockPC != fetchBufferPC[tid])
1236 break;
1237
1238 if (blkOffset >= numInsts) {
1239 // We need to process more memory, but we've run out of the
1240 // current block.
1241 break;
1242 }
1243

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1323 newMacro |= thisPC.instAddr() != nextPC.instAddr();
1324
1325 // Move to the next instruction, unless we have a branch.
1326 thisPC = nextPC;
1327 inRom = isRomMicroPC(thisPC.microPC());
1328
1329 if (newMacro) {
1330 fetchAddr = thisPC.instAddr() & BaseCPU::PCMask;
1246 break;
1247
1248 if (blkOffset >= numInsts) {
1249 // We need to process more memory, but we've run out of the
1250 // current block.
1251 break;
1252 }
1253

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1333 newMacro |= thisPC.instAddr() != nextPC.instAddr();
1334
1335 // Move to the next instruction, unless we have a branch.
1336 thisPC = nextPC;
1337 inRom = isRomMicroPC(thisPC.microPC());
1338
1339 if (newMacro) {
1340 fetchAddr = thisPC.instAddr() & BaseCPU::PCMask;
1331 blkOffset = (fetchAddr - cacheDataPC[tid]) / instSize;
1341 blkOffset = (fetchAddr - fetchBufferPC[tid]) / instSize;
1332 pcOffset = 0;
1333 curMacroop = NULL;
1334 }
1335
1336 if (instruction->isQuiesce()) {
1337 DPRINTF(Fetch,
1338 "Quiesce instruction encountered, halting fetch!");
1339 fetchStatus[tid] = QuiescePending;

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1345 }
1346
1347 if (predictedBranch) {
1348 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1349 "instruction encountered.\n", tid);
1350 } else if (numInst >= fetchWidth) {
1351 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1352 "for this cycle.\n", tid);
1342 pcOffset = 0;
1343 curMacroop = NULL;
1344 }
1345
1346 if (instruction->isQuiesce()) {
1347 DPRINTF(Fetch,
1348 "Quiesce instruction encountered, halting fetch!");
1349 fetchStatus[tid] = QuiescePending;

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1355 }
1356
1357 if (predictedBranch) {
1358 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1359 "instruction encountered.\n", tid);
1360 } else if (numInst >= fetchWidth) {
1361 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1362 "for this cycle.\n", tid);
1353 } else if (blkOffset >= cacheBlkSize) {
1354 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
1355 "block.\n", tid);
1363 } else if (blkOffset >= fetchBufferSize) {
1364 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of the"
1365 "fetch buffer.\n", tid);
1356 }
1357
1358 macroop[tid] = curMacroop;
1359 fetchOffset[tid] = pcOffset;
1360
1361 if (numInst > 0) {
1362 wroteToTimeBuffer = true;
1363 }
1364
1365 pc[tid] = thisPC;
1366
1366 }
1367
1368 macroop[tid] = curMacroop;
1369 fetchOffset[tid] = pcOffset;
1370
1371 if (numInst > 0) {
1372 wroteToTimeBuffer = true;
1373 }
1374
1375 pc[tid] = thisPC;
1376
1367 // pipeline a fetch if we're crossing a cache boundary and not in
1377 // pipeline a fetch if we're crossing a fetch buffer boundary and not in
1368 // a state that would preclude fetching
1369 fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
1378 // a state that would preclude fetching
1379 fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
1370 Addr block_PC = icacheBlockAlignPC(fetchAddr);
1371 issuePipelinedIfetch[tid] = block_PC != cacheDataPC[tid] &&
1380 Addr fetchBufferBlockPC = fetchBufferAlignPC(fetchAddr);
1381 issuePipelinedIfetch[tid] = fetchBufferBlockPC != fetchBufferPC[tid] &&
1372 fetchStatus[tid] != IcacheWaitResponse &&
1373 fetchStatus[tid] != ItlbWait &&
1374 fetchStatus[tid] != IcacheWaitRetry &&
1375 fetchStatus[tid] != QuiescePending &&
1376 !curMacroop;
1377}
1378
1379template<class Impl>

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1570
1571 if (isRomMicroPC(thisPC.microPC())) {
1572 return;
1573 }
1574
1575 Addr pcOffset = fetchOffset[tid];
1576 Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
1577
1382 fetchStatus[tid] != IcacheWaitResponse &&
1383 fetchStatus[tid] != ItlbWait &&
1384 fetchStatus[tid] != IcacheWaitRetry &&
1385 fetchStatus[tid] != QuiescePending &&
1386 !curMacroop;
1387}
1388
1389template<class Impl>

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1580
1581 if (isRomMicroPC(thisPC.microPC())) {
1582 return;
1583 }
1584
1585 Addr pcOffset = fetchOffset[tid];
1586 Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
1587
1578 // Align the fetch PC so its at the start of a cache block.
1579 Addr block_PC = icacheBlockAlignPC(fetchAddr);
1588 // Align the fetch PC so its at the start of a fetch buffer segment.
1589 Addr fetchBufferBlockPC = fetchBufferAlignPC(fetchAddr);
1580
1581 // Unless buffer already got the block, fetch it from icache.
1590
1591 // Unless buffer already got the block, fetch it from icache.
1582 if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid])) {
1592 if (!(fetchBufferValid[tid] && fetchBufferBlockPC == fetchBufferPC[tid])) {
1583 DPRINTF(Fetch, "[tid:%i]: Issuing a pipelined I-cache access, "
1584 "starting at PC %s.\n", tid, thisPC);
1585
1586 fetchCacheLine(fetchAddr, tid, thisPC.instAddr());
1587 }
1588}
1589
1590template<class Impl>

--- 48 unchanged lines hidden --- 		1593 DPRINTF(Fetch, "[tid:%i]: Issuing a pipelined I-cache access, "
1594 "starting at PC %s.\n", tid, thisPC);
1595
1596 fetchCacheLine(fetchAddr, tid, thisPC.instAddr());
1597 }
1598}
1599
1600template<class Impl>

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