fetch_impl.hh (9644:07352f119e48) | fetch_impl.hh (9814:7ad2b0186a32) |
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1/* | 1/* |
2 * Copyright (c) 2010-2012 ARM Limited | 2 * Copyright (c) 2010-2013 ARM Limited |
3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 65 unchanged lines hidden (view full) --- 76 : cpu(_cpu), 77 decodeToFetchDelay(params->decodeToFetchDelay), 78 renameToFetchDelay(params->renameToFetchDelay), 79 iewToFetchDelay(params->iewToFetchDelay), 80 commitToFetchDelay(params->commitToFetchDelay), 81 fetchWidth(params->fetchWidth), 82 retryPkt(NULL), 83 retryTid(InvalidThreadID), | 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 65 unchanged lines hidden (view full) --- 76 : cpu(_cpu), 77 decodeToFetchDelay(params->decodeToFetchDelay), 78 renameToFetchDelay(params->renameToFetchDelay), 79 iewToFetchDelay(params->iewToFetchDelay), 80 commitToFetchDelay(params->commitToFetchDelay), 81 fetchWidth(params->fetchWidth), 82 retryPkt(NULL), 83 retryTid(InvalidThreadID), |
84 cacheBlkSize(cpu->cacheLineSize()), 85 cacheBlkMask(cacheBlkSize - 1), |
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84 numThreads(params->numThreads), 85 numFetchingThreads(params->smtNumFetchingThreads), 86 finishTranslationEvent(this) 87{ 88 if (numThreads > Impl::MaxThreads) 89 fatal("numThreads (%d) is larger than compiled limit (%d),\n" 90 "\tincrease MaxThreads in src/cpu/o3/impl.hh\n", 91 numThreads, static_cast<int>(Impl::MaxThreads)); --- 29 unchanged lines hidden (view full) --- 121 fatal("Invalid Fetch Policy. Options Are: {SingleThread," 122 " RoundRobin,LSQcount,IQcount}\n"); 123 } 124 125 // Get the size of an instruction. 126 instSize = sizeof(TheISA::MachInst); 127 128 for (int i = 0; i < Impl::MaxThreads; i++) { | 86 numThreads(params->numThreads), 87 numFetchingThreads(params->smtNumFetchingThreads), 88 finishTranslationEvent(this) 89{ 90 if (numThreads > Impl::MaxThreads) 91 fatal("numThreads (%d) is larger than compiled limit (%d),\n" 92 "\tincrease MaxThreads in src/cpu/o3/impl.hh\n", 93 numThreads, static_cast<int>(Impl::MaxThreads)); --- 29 unchanged lines hidden (view full) --- 123 fatal("Invalid Fetch Policy. Options Are: {SingleThread," 124 " RoundRobin,LSQcount,IQcount}\n"); 125 } 126 127 // Get the size of an instruction. 128 instSize = sizeof(TheISA::MachInst); 129 130 for (int i = 0; i < Impl::MaxThreads; i++) { |
129 cacheData[i] = NULL; | |
130 decoder[i] = new TheISA::Decoder; 131 } 132 133 branchPred = params->branchPred; | 131 decoder[i] = new TheISA::Decoder; 132 } 133 134 branchPred = params->branchPred; |
135 136 for (ThreadID tid = 0; tid < numThreads; tid++) { 137 // Create space to store a cache line. 138 cacheData[tid] = new uint8_t[cacheBlkSize]; 139 cacheDataPC[tid] = 0; 140 cacheDataValid[tid] = false; 141 } |
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134} 135 136template <class Impl> 137std::string 138DefaultFetch<Impl>::name() const 139{ 140 return cpu->name() + ".fetch"; 141} --- 189 unchanged lines hidden (view full) --- 331 stalls[tid].commit = false; 332 stalls[tid].drain = false; 333 334 priorityList.push_back(tid); 335 } 336 337 wroteToTimeBuffer = false; 338 _status = Inactive; | 142} 143 144template <class Impl> 145std::string 146DefaultFetch<Impl>::name() const 147{ 148 return cpu->name() + ".fetch"; 149} --- 189 unchanged lines hidden (view full) --- 339 stalls[tid].commit = false; 340 stalls[tid].drain = false; 341 342 priorityList.push_back(tid); 343 } 344 345 wroteToTimeBuffer = false; 346 _status = Inactive; |
339 340 // this CPU could still be unconnected if we are restoring from a 341 // checkpoint and this CPU is to be switched in, thus we can only 342 // do this here if the instruction port is actually connected, if 343 // not we have to do it as part of takeOverFrom. 344 if (cpu->getInstPort().isConnected()) 345 setIcache(); | |
346} 347 348template<class Impl> 349void | 347} 348 349template<class Impl> 350void |
350DefaultFetch<Impl>::setIcache() 351{ 352 assert(cpu->getInstPort().isConnected()); 353 354 // Size of cache block. 355 cacheBlkSize = cpu->getInstPort().peerBlockSize(); 356 357 // Create mask to get rid of offset bits. 358 cacheBlkMask = (cacheBlkSize - 1); 359 360 for (ThreadID tid = 0; tid < numThreads; tid++) { 361 // Create space to store a cache line. 362 if (!cacheData[tid]) 363 cacheData[tid] = new uint8_t[cacheBlkSize]; 364 cacheDataPC[tid] = 0; 365 cacheDataValid[tid] = false; 366 } 367} 368 369template<class Impl> 370void | |
371DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) 372{ 373 ThreadID tid = pkt->req->threadId(); 374 375 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n", tid); 376 assert(!cpu->switchedOut()); 377 378 // Only change the status if it's still waiting on the icache access --- 1270 unchanged lines hidden --- | 351DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) 352{ 353 ThreadID tid = pkt->req->threadId(); 354 355 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n", tid); 356 assert(!cpu->switchedOut()); 357 358 // Only change the status if it's still waiting on the icache access --- 1270 unchanged lines hidden --- |