fetch_impl.hh (9444:ab47fe7f03f0) fetch_impl.hh (9480:d059f8a95a42)
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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68#include "sim/full_system.hh"
69#include "sim/system.hh"
70
71using namespace std;
72
73template<class Impl>
74DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
75 : cpu(_cpu),
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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68#include "sim/full_system.hh"
69#include "sim/system.hh"
70
71using namespace std;
72
73template<class Impl>
74DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
75 : cpu(_cpu),
76 branchPred(params),
77 decodeToFetchDelay(params->decodeToFetchDelay),
78 renameToFetchDelay(params->renameToFetchDelay),
79 iewToFetchDelay(params->iewToFetchDelay),
80 commitToFetchDelay(params->commitToFetchDelay),
81 fetchWidth(params->fetchWidth),
82 retryPkt(NULL),
83 retryTid(InvalidThreadID),
84 numThreads(params->numThreads),

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124
125 // Get the size of an instruction.
126 instSize = sizeof(TheISA::MachInst);
127
128 for (int i = 0; i < Impl::MaxThreads; i++) {
129 cacheData[i] = NULL;
130 decoder[i] = new TheISA::Decoder;
131 }
76 decodeToFetchDelay(params->decodeToFetchDelay),
77 renameToFetchDelay(params->renameToFetchDelay),
78 iewToFetchDelay(params->iewToFetchDelay),
79 commitToFetchDelay(params->commitToFetchDelay),
80 fetchWidth(params->fetchWidth),
81 retryPkt(NULL),
82 retryTid(InvalidThreadID),
83 numThreads(params->numThreads),

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123
124 // Get the size of an instruction.
125 instSize = sizeof(TheISA::MachInst);
126
127 for (int i = 0; i < Impl::MaxThreads; i++) {
128 cacheData[i] = NULL;
129 decoder[i] = new TheISA::Decoder;
130 }
131
132 branchPred = params->branchPred;
132}
133
134template <class Impl>
135std::string
136DefaultFetch<Impl>::name() const
137{
138 return cpu->name() + ".fetch";
139}

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254 .flags(Stats::total);
255 branchRate = fetchedBranches / cpu->numCycles;
256
257 fetchRate
258 .name(name() + ".rate")
259 .desc("Number of inst fetches per cycle")
260 .flags(Stats::total);
261 fetchRate = fetchedInsts / cpu->numCycles;
133}
134
135template <class Impl>
136std::string
137DefaultFetch<Impl>::name() const
138{
139 return cpu->name() + ".fetch";
140}

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255 .flags(Stats::total);
256 branchRate = fetchedBranches / cpu->numCycles;
257
258 fetchRate
259 .name(name() + ".rate")
260 .desc("Number of inst fetches per cycle")
261 .flags(Stats::total);
262 fetchRate = fetchedInsts / cpu->numCycles;
262
263 branchPred.regStats();
264}
265
266template<class Impl>
267void
268DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
269{
270 timeBuffer = time_buffer;
271

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432 assert(!memReq[i]);
433 assert(!stalls[i].decode);
434 assert(!stalls[i].rename);
435 assert(!stalls[i].iew);
436 assert(!stalls[i].commit);
437 assert(fetchStatus[i] == Idle || stalls[i].drain);
438 }
439
263}
264
265template<class Impl>
266void
267DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
268{
269 timeBuffer = time_buffer;
270

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431 assert(!memReq[i]);
432 assert(!stalls[i].decode);
433 assert(!stalls[i].rename);
434 assert(!stalls[i].iew);
435 assert(!stalls[i].commit);
436 assert(fetchStatus[i] == Idle || stalls[i].drain);
437 }
438
440 branchPred.drainSanityCheck();
439 branchPred->drainSanityCheck();
441}
442
443template <class Impl>
444bool
445DefaultFetch<Impl>::isDrained() const
446{
447 /* Make sure that threads are either idle of that the commit stage
448 * has signaled that draining has completed by setting the drain

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465
466template <class Impl>
467void
468DefaultFetch<Impl>::takeOverFrom()
469{
470 assert(cpu->getInstPort().isConnected());
471 resetStage();
472
440}
441
442template <class Impl>
443bool
444DefaultFetch<Impl>::isDrained() const
445{
446 /* Make sure that threads are either idle of that the commit stage
447 * has signaled that draining has completed by setting the drain

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464
465template <class Impl>
466void
467DefaultFetch<Impl>::takeOverFrom()
468{
469 assert(cpu->getInstPort().isConnected());
470 resetStage();
471
473 branchPred.takeOverFrom();
474}
475
476template <class Impl>
477void
478DefaultFetch<Impl>::drainStall(ThreadID tid)
479{
480 assert(cpu->isDraining());
481 assert(!stalls[tid].drain);

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532 if (!inst->isControl()) {
533 TheISA::advancePC(nextPC, inst->staticInst);
534 inst->setPredTarg(nextPC);
535 inst->setPredTaken(false);
536 return false;
537 }
538
539 ThreadID tid = inst->threadNumber;
472}
473
474template <class Impl>
475void
476DefaultFetch<Impl>::drainStall(ThreadID tid)
477{
478 assert(cpu->isDraining());
479 assert(!stalls[tid].drain);

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530 if (!inst->isControl()) {
531 TheISA::advancePC(nextPC, inst->staticInst);
532 inst->setPredTarg(nextPC);
533 inst->setPredTaken(false);
534 return false;
535 }
536
537 ThreadID tid = inst->threadNumber;
540 predict_taken = branchPred.predict(inst, nextPC, tid);
538 predict_taken = branchPred->predict(inst->staticInst, inst->seqNum,
539 nextPC, tid);
541
542 if (predict_taken) {
543 DPRINTF(Fetch, "[tid:%i]: [sn:%i]: Branch predicted to be taken to %s.\n",
544 tid, inst->seqNum, nextPC);
545 } else {
546 DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not taken.\n",
547 tid, inst->seqNum);
548 }

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985 fromCommit->commitInfo[tid].doneSeqNum,
986 fromCommit->commitInfo[tid].squashInst, tid);
987
988 // If it was a branch mispredict on a control instruction, update the
989 // branch predictor with that instruction, otherwise just kill the
990 // invalid state we generated in after sequence number
991 if (fromCommit->commitInfo[tid].mispredictInst &&
992 fromCommit->commitInfo[tid].mispredictInst->isControl()) {
540
541 if (predict_taken) {
542 DPRINTF(Fetch, "[tid:%i]: [sn:%i]: Branch predicted to be taken to %s.\n",
543 tid, inst->seqNum, nextPC);
544 } else {
545 DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not taken.\n",
546 tid, inst->seqNum);
547 }

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984 fromCommit->commitInfo[tid].doneSeqNum,
985 fromCommit->commitInfo[tid].squashInst, tid);
986
987 // If it was a branch mispredict on a control instruction, update the
988 // branch predictor with that instruction, otherwise just kill the
989 // invalid state we generated in after sequence number
990 if (fromCommit->commitInfo[tid].mispredictInst &&
991 fromCommit->commitInfo[tid].mispredictInst->isControl()) {
993 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
992 branchPred->squash(fromCommit->commitInfo[tid].doneSeqNum,
994 fromCommit->commitInfo[tid].pc,
995 fromCommit->commitInfo[tid].branchTaken,
996 tid);
997 } else {
993 fromCommit->commitInfo[tid].pc,
994 fromCommit->commitInfo[tid].branchTaken,
995 tid);
996 } else {
998 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
997 branchPred->squash(fromCommit->commitInfo[tid].doneSeqNum,
999 tid);
1000 }
1001
1002 return true;
1003 } else if (fromCommit->commitInfo[tid].doneSeqNum) {
1004 // Update the branch predictor if it wasn't a squashed instruction
1005 // that was broadcasted.
998 tid);
999 }
1000
1001 return true;
1002 } else if (fromCommit->commitInfo[tid].doneSeqNum) {
1003 // Update the branch predictor if it wasn't a squashed instruction
1004 // that was broadcasted.
1006 branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
1005 branchPred->update(fromCommit->commitInfo[tid].doneSeqNum, tid);
1007 }
1008
1009 // Check ROB squash signals from commit.
1010 if (fromCommit->commitInfo[tid].robSquashing) {
1011 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
1012
1013 // Continue to squash.
1014 fetchStatus[tid] = Squashing;
1015
1016 return true;
1017 }
1018
1019 // Check squash signals from decode.
1020 if (fromDecode->decodeInfo[tid].squash) {
1021 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
1022 "from decode.\n",tid);
1023
1024 // Update the branch predictor.
1025 if (fromDecode->decodeInfo[tid].branchMispredict) {
1006 }
1007
1008 // Check ROB squash signals from commit.
1009 if (fromCommit->commitInfo[tid].robSquashing) {
1010 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
1011
1012 // Continue to squash.
1013 fetchStatus[tid] = Squashing;
1014
1015 return true;
1016 }
1017
1018 // Check squash signals from decode.
1019 if (fromDecode->decodeInfo[tid].squash) {
1020 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
1021 "from decode.\n",tid);
1022
1023 // Update the branch predictor.
1024 if (fromDecode->decodeInfo[tid].branchMispredict) {
1026 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
1025 branchPred->squash(fromDecode->decodeInfo[tid].doneSeqNum,
1027 fromDecode->decodeInfo[tid].nextPC,
1028 fromDecode->decodeInfo[tid].branchTaken,
1029 tid);
1030 } else {
1026 fromDecode->decodeInfo[tid].nextPC,
1027 fromDecode->decodeInfo[tid].branchTaken,
1028 tid);
1029 } else {
1031 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
1030 branchPred->squash(fromDecode->decodeInfo[tid].doneSeqNum,
1032 tid);
1033 }
1034
1035 if (fetchStatus[tid] != Squashing) {
1036
1037 DPRINTF(Fetch, "Squashing from decode with PC = %s\n",
1038 fromDecode->decodeInfo[tid].nextPC);
1039 // Squash unless we're already squashing

--- 605 unchanged lines hidden --- 		1031 tid);
1032 }
1033
1034 if (fetchStatus[tid] != Squashing) {
1035
1036 DPRINTF(Fetch, "Squashing from decode with PC = %s\n",
1037 fromDecode->decodeInfo[tid].nextPC);
1038 // Squash unless we're already squashing

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