fetch_impl.hh (8832:247fee427324) fetch_impl.hh (8850:ed91b534ed04)
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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330 // so it must start up in active state.
331 switchToActive();
332}
333
334template<class Impl>
335void
336DefaultFetch<Impl>::setIcache()
337{
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 321 unchanged lines hidden (view full) ---

330 // so it must start up in active state.
331 switchToActive();
332}
333
334template<class Impl>
335void
336DefaultFetch<Impl>::setIcache()
337{
338 assert(cpu->getIcachePort()->isConnected());
338 assert(cpu->getInstPort().isConnected());
339
340 // Size of cache block.
339
340 // Size of cache block.
341 cacheBlkSize = cpu->getIcachePort()->peerBlockSize();
341 cacheBlkSize = cpu->getInstPort().peerBlockSize();
342
343 // Create mask to get rid of offset bits.
344 cacheBlkMask = (cacheBlkSize - 1);
345
346 for (ThreadID tid = 0; tid < numThreads; tid++) {
347 // Create space to store a cache line.
348 cacheData[tid] = new uint8_t[cacheBlkSize];
349 cacheDataPC[tid] = 0;

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618
619 cacheDataPC[tid] = block_PC;
620 cacheDataValid[tid] = false;
621 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
622
623 fetchedCacheLines++;
624
625 // Access the cache.
342
343 // Create mask to get rid of offset bits.
344 cacheBlkMask = (cacheBlkSize - 1);
345
346 for (ThreadID tid = 0; tid < numThreads; tid++) {
347 // Create space to store a cache line.
348 cacheData[tid] = new uint8_t[cacheBlkSize];
349 cacheDataPC[tid] = 0;

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618
619 cacheDataPC[tid] = block_PC;
620 cacheDataValid[tid] = false;
621 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
622
623 fetchedCacheLines++;
624
625 // Access the cache.
626 if (!cpu->getIcachePort()->sendTiming(data_pkt)) {
626 if (!cpu->getInstPort().sendTiming(data_pkt)) {
627 assert(retryPkt == NULL);
628 assert(retryTid == InvalidThreadID);
629 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
630
631 fetchStatus[tid] = IcacheWaitRetry;
632 retryPkt = data_pkt;
633 retryTid = tid;
634 cacheBlocked = true;

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1353void
1354DefaultFetch<Impl>::recvRetry()
1355{
1356 if (retryPkt != NULL) {
1357 assert(cacheBlocked);
1358 assert(retryTid != InvalidThreadID);
1359 assert(fetchStatus[retryTid] == IcacheWaitRetry);
1360
627 assert(retryPkt == NULL);
628 assert(retryTid == InvalidThreadID);
629 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
630
631 fetchStatus[tid] = IcacheWaitRetry;
632 retryPkt = data_pkt;
633 retryTid = tid;
634 cacheBlocked = true;

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1353void
1354DefaultFetch<Impl>::recvRetry()
1355{
1356 if (retryPkt != NULL) {
1357 assert(cacheBlocked);
1358 assert(retryTid != InvalidThreadID);
1359 assert(fetchStatus[retryTid] == IcacheWaitRetry);
1360
1361 if (cpu->getIcachePort()->sendTiming(retryPkt)) {
1361 if (cpu->getInstPort().sendTiming(retryPkt)) {
1362 fetchStatus[retryTid] = IcacheWaitResponse;
1363 retryPkt = NULL;
1364 retryTid = InvalidThreadID;
1365 cacheBlocked = false;
1366 }
1367 } else {
1368 assert(retryTid == InvalidThreadID);
1369 // Access has been squashed since it was sent out. Just clear

--- 240 unchanged lines hidden --- 		1362 fetchStatus[retryTid] = IcacheWaitResponse;
1363 retryPkt = NULL;
1364 retryTid = InvalidThreadID;
1365 cacheBlocked = false;
1366 }
1367 } else {
1368 assert(retryTid == InvalidThreadID);
1369 // Access has been squashed since it was sent out. Just clear

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