fetch_impl.hh (8824:a42647b4a6b6) fetch_impl.hh (8832:247fee427324)
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 551 unchanged lines hidden (view full) ---

560 DPRINTF(Fetch, "[tid:%i] Fetching cache line %#x for addr %#x\n",
561 tid, block_PC, vaddr);
562
563 // Setup the memReq to do a read of the first instruction's address.
564 // Set the appropriate read size and flags as well.
565 // Build request here.
566 RequestPtr mem_req =
567 new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH,
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 551 unchanged lines hidden (view full) ---

560 DPRINTF(Fetch, "[tid:%i] Fetching cache line %#x for addr %#x\n",
561 tid, block_PC, vaddr);
562
563 // Setup the memReq to do a read of the first instruction's address.
564 // Set the appropriate read size and flags as well.
565 // Build request here.
566 RequestPtr mem_req =
567 new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH,
568 pc, cpu->thread[tid]->contextId(), tid);
568 cpu->instMasterId(), pc, cpu->thread[tid]->contextId(), tid);
569
570 memReq[tid] = mem_req;
571
572 // Initiate translation of the icache block
573 fetchStatus[tid] = ItlbWait;
574 FetchTranslation *trans = new FetchTranslation(this);
575 cpu->itb->translateTiming(mem_req, cpu->thread[tid]->getTC(),
576 trans, BaseTLB::Execute);

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570 memReq[tid] = mem_req;
571
572 // Initiate translation of the icache block
573 fetchStatus[tid] = ItlbWait;
574 FetchTranslation *trans = new FetchTranslation(this);
575 cpu->itb->translateTiming(mem_req, cpu->thread[tid]->getTC(),
576 trans, BaseTLB::Execute);

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