fetch_impl.hh (8641:4d3ecac1abec) fetch_impl.hh (8707:489489c67fd9)
1/*
1/*
2 * Copyright (c) 2010 ARM Limited
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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66#include "arch/tlb.hh"
67#include "arch/vtophys.hh"
68#include "sim/system.hh"
69#endif // FULL_SYSTEM
70
71using namespace std;
72
73template<class Impl>
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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66#include "arch/tlb.hh"
67#include "arch/vtophys.hh"
68#include "sim/system.hh"
69#endif // FULL_SYSTEM
70
71using namespace std;
72
73template<class Impl>
74void
75DefaultFetch<Impl>::IcachePort::setPeer(Port *port)
76{
77 Port::setPeer(port);
78
79 fetch->setIcache();
80}
81
82template<class Impl>
83Tick
84DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
85{
86 panic("DefaultFetch doesn't expect recvAtomic callback!");
87 return curTick();
88}
89
90template<class Impl>
91void
92DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
93{
94 DPRINTF(Fetch, "DefaultFetch doesn't update its state from a "
95 "functional call.\n");
96}
97
98template<class Impl>
99void
100DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
101{
102 if (status == RangeChange) {
103 if (!snoopRangeSent) {
104 snoopRangeSent = true;
105 sendStatusChange(Port::RangeChange);
106 }
107 return;
108 }
109
110 panic("DefaultFetch doesn't expect recvStatusChange callback!");
111}
112
113template<class Impl>
114bool
115DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
116{
117 DPRINTF(Fetch, "Received timing\n");
118 if (pkt->isResponse()) {
119 // We shouldn't ever get a block in ownership state
120 assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
121
122 fetch->processCacheCompletion(pkt);
123 }
124 //else Snooped a coherence request, just return
125 return true;
126}
127
128template<class Impl>
129void
130DefaultFetch<Impl>::IcachePort::recvRetry()
131{
132 fetch->recvRetry();
133}
134
135template<class Impl>
136DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
137 : cpu(_cpu),
138 branchPred(params),
139 predecoder(NULL),
140 numInst(0),
141 decodeToFetchDelay(params->decodeToFetchDelay),
142 renameToFetchDelay(params->renameToFetchDelay),
143 iewToFetchDelay(params->iewToFetchDelay),

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186 DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
187 } else {
188 fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
189 " RoundRobin,LSQcount,IQcount}\n");
190 }
191
192 // Get the size of an instruction.
193 instSize = sizeof(TheISA::MachInst);
74DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
75 : cpu(_cpu),
76 branchPred(params),
77 predecoder(NULL),
78 numInst(0),
79 decodeToFetchDelay(params->decodeToFetchDelay),
80 renameToFetchDelay(params->renameToFetchDelay),
81 iewToFetchDelay(params->iewToFetchDelay),

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124 DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
125 } else {
126 fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
127 " RoundRobin,LSQcount,IQcount}\n");
128 }
129
130 // Get the size of an instruction.
131 instSize = sizeof(TheISA::MachInst);
194
195 // Name is finally available, so create the port.
196 icachePort = new IcachePort(this);
197
198 icachePort->snoopRangeSent = false;
199
200#if USE_CHECKER
201 if (cpu->checker) {
202 cpu->checker->setIcachePort(icachePort);
203 }
204#endif
205}
206
207template <class Impl>
208std::string
209DefaultFetch<Impl>::name() const
210{
211 return cpu->name() + ".fetch";
212}

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399 // so it must start up in active state.
400 switchToActive();
401}
402
403template<class Impl>
404void
405DefaultFetch<Impl>::setIcache()
406{
132}
133
134template <class Impl>
135std::string
136DefaultFetch<Impl>::name() const
137{
138 return cpu->name() + ".fetch";
139}

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326 // so it must start up in active state.
327 switchToActive();
328}
329
330template<class Impl>
331void
332DefaultFetch<Impl>::setIcache()
333{
334 assert(cpu->getIcachePort()->isConnected());
335
407 // Size of cache block.
336 // Size of cache block.
408 cacheBlkSize = icachePort->peerBlockSize();
337 cacheBlkSize = cpu->getIcachePort()->peerBlockSize();
409
410 // Create mask to get rid of offset bits.
411 cacheBlkMask = (cacheBlkSize - 1);
412
413 for (ThreadID tid = 0; tid < numThreads; tid++) {
414 // Create space to store a cache line.
415 cacheData[tid] = new uint8_t[cacheBlkSize];
416 cacheDataPC[tid] = 0;

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491 // Branch predictor needs to have its state cleared.
492 branchPred.switchOut();
493}
494
495template <class Impl>
496void
497DefaultFetch<Impl>::takeOverFrom()
498{
338
339 // Create mask to get rid of offset bits.
340 cacheBlkMask = (cacheBlkSize - 1);
341
342 for (ThreadID tid = 0; tid < numThreads; tid++) {
343 // Create space to store a cache line.
344 cacheData[tid] = new uint8_t[cacheBlkSize];
345 cacheDataPC[tid] = 0;

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420 // Branch predictor needs to have its state cleared.
421 branchPred.switchOut();
422}
423
424template <class Impl>
425void
426DefaultFetch<Impl>::takeOverFrom()
427{
428 // the instruction port is now connected so we can get the block
429 // size
430 setIcache();
431
499 // Reset all state
500 for (ThreadID i = 0; i < Impl::MaxThreads; ++i) {
501 stalls[i].decode = 0;
502 stalls[i].rename = 0;
503 stalls[i].iew = 0;
504 stalls[i].commit = 0;
505 pc[i] = cpu->pcState(i);
506 fetchStatus[i] = Running;

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681
682 cacheDataPC[tid] = block_PC;
683 cacheDataValid[tid] = false;
684 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
685
686 fetchedCacheLines++;
687
688 // Access the cache.
432 // Reset all state
433 for (ThreadID i = 0; i < Impl::MaxThreads; ++i) {
434 stalls[i].decode = 0;
435 stalls[i].rename = 0;
436 stalls[i].iew = 0;
437 stalls[i].commit = 0;
438 pc[i] = cpu->pcState(i);
439 fetchStatus[i] = Running;

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614
615 cacheDataPC[tid] = block_PC;
616 cacheDataValid[tid] = false;
617 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
618
619 fetchedCacheLines++;
620
621 // Access the cache.
689 if (!icachePort->sendTiming(data_pkt)) {
622 if (!cpu->getIcachePort()->sendTiming(data_pkt)) {
690 assert(retryPkt == NULL);
691 assert(retryTid == InvalidThreadID);
692 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
693
694 fetchStatus[tid] = IcacheWaitRetry;
695 retryPkt = data_pkt;
696 retryTid = tid;
697 cacheBlocked = true;

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1400void
1401DefaultFetch<Impl>::recvRetry()
1402{
1403 if (retryPkt != NULL) {
1404 assert(cacheBlocked);
1405 assert(retryTid != InvalidThreadID);
1406 assert(fetchStatus[retryTid] == IcacheWaitRetry);
1407
623 assert(retryPkt == NULL);
624 assert(retryTid == InvalidThreadID);
625 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
626
627 fetchStatus[tid] = IcacheWaitRetry;
628 retryPkt = data_pkt;
629 retryTid = tid;
630 cacheBlocked = true;

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1333void
1334DefaultFetch<Impl>::recvRetry()
1335{
1336 if (retryPkt != NULL) {
1337 assert(cacheBlocked);
1338 assert(retryTid != InvalidThreadID);
1339 assert(fetchStatus[retryTid] == IcacheWaitRetry);
1340
1408 if (icachePort->sendTiming(retryPkt)) {
1341 if (cpu->getIcachePort()->sendTiming(retryPkt)) {
1409 fetchStatus[retryTid] = IcacheWaitResponse;
1410 retryPkt = NULL;
1411 retryTid = InvalidThreadID;
1412 cacheBlocked = false;
1413 }
1414 } else {
1415 assert(retryTid == InvalidThreadID);
1416 // Access has been squashed since it was sent out. Just clear

--- 240 unchanged lines hidden --- 		1342 fetchStatus[retryTid] = IcacheWaitResponse;
1343 retryPkt = NULL;
1344 retryTid = InvalidThreadID;
1345 cacheBlocked = false;
1346 }
1347 } else {
1348 assert(retryTid == InvalidThreadID);
1349 // Access has been squashed since it was sent out. Just clear

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