fetch_impl.hh (8499:e5f14b00c0ae) fetch_impl.hh (8502:f1fc7102c970)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1092 StaticInstPtr curMacroop, TheISA::PCState thisPC,
1093 TheISA::PCState nextPC, bool trace)
1094{
1095 // Get a sequence number.
1096 InstSeqNum seq = cpu->getAndIncrementInstSeq();
1097
1098 // Create a new DynInst from the instruction fetched.
1099 DynInstPtr instruction =
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 1083 unchanged lines hidden (view full) ---

1092 StaticInstPtr curMacroop, TheISA::PCState thisPC,
1093 TheISA::PCState nextPC, bool trace)
1094{
1095 // Get a sequence number.
1096 InstSeqNum seq = cpu->getAndIncrementInstSeq();
1097
1098 // Create a new DynInst from the instruction fetched.
1099 DynInstPtr instruction =
1100 new DynInst(staticInst, thisPC, nextPC, seq, cpu);
1100 new DynInst(staticInst, curMacroop, thisPC, nextPC, seq, cpu);
1101 instruction->setTid(tid);
1102
1103 instruction->setASID(tid);
1104
1105 instruction->setThreadState(cpu->thread[tid]);
1106
1107 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x (%d) created "
1108 "[sn:%lli].\n", tid, thisPC.instAddr(),

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1101 instruction->setTid(tid);
1102
1103 instruction->setASID(tid);
1104
1105 instruction->setThreadState(cpu->thread[tid]);
1106
1107 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x (%d) created "
1108 "[sn:%lli].\n", tid, thisPC.instAddr(),

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