fetch_impl.hh (8346:ce8b9a250021) fetch_impl.hh (8460:3893d9d2c6c2)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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628 ++fetchTlbSquashes;
629 delete mem_req;
630 return;
631 }
632
633
634 // If translation was successful, attempt to read the icache block.
635 if (fault == NoFault) {
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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628 ++fetchTlbSquashes;
629 delete mem_req;
630 return;
631 }
632
633
634 // If translation was successful, attempt to read the icache block.
635 if (fault == NoFault) {
636 // Check that we're not going off into random memory
637 // If we have, just wait around for commit to squash something and put
638 // us on the right track
639 if (!cpu->system->isMemory(mem_req->getPaddr())) {
640 warn("Address %#x is outside of physical memory, stopping fetch\n",
641 mem_req->getPaddr());
642 fetchStatus[tid] = NoGoodAddr;
643 delete mem_req;
644 memReq[tid] = NULL;
645 return;
646 }
647
636 // Build packet here.
637 PacketPtr data_pkt = new Packet(mem_req,
638 MemCmd::ReadReq, Packet::Broadcast);
639 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
640
641 cacheDataPC[tid] = block_PC;
642 cacheDataValid[tid] = false;
643 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");

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1157 tid);
1158 } else if (fetchStatus[tid] == ItlbWait) {
1159 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting ITLB walk to "
1160 "finish! \n", tid);
1161 ++fetchTlbCycles;
1162 } else if (fetchStatus[tid] == TrapPending) {
1163 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending trap\n",
1164 tid);
648 // Build packet here.
649 PacketPtr data_pkt = new Packet(mem_req,
650 MemCmd::ReadReq, Packet::Broadcast);
651 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
652
653 cacheDataPC[tid] = block_PC;
654 cacheDataValid[tid] = false;
655 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");

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1169 tid);
1170 } else if (fetchStatus[tid] == ItlbWait) {
1171 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting ITLB walk to "
1172 "finish! \n", tid);
1173 ++fetchTlbCycles;
1174 } else if (fetchStatus[tid] == TrapPending) {
1175 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending trap\n",
1176 tid);
1177 } else if (fetchStatus[tid] == NoGoodAddr) {
1178 DPRINTF(Fetch, "[tid:%i]: Fetch predicted non-executable address\n",
1179 tid);
1165 }
1166
1167
1180 }
1181
1182
1183
1168 // Status is Idle, Squashing, Blocked, ItlbWait or IcacheWaitResponse
1169 // so fetch should do nothing.
1170 return;
1171 }
1172
1173 ++fetchCycles;
1174
1175 TheISA::PCState nextPC = thisPC;

--- 322 unchanged lines hidden --- 		1184 // Status is Idle, Squashing, Blocked, ItlbWait or IcacheWaitResponse
1185 // so fetch should do nothing.
1186 return;
1187 }
1188
1189 ++fetchCycles;
1190
1191 TheISA::PCState nextPC = thisPC;

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