fetch_impl.hh (8232:b28d06a175be) fetch_impl.hh (8314:13ac7b9939ef)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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341void
342DefaultFetch<Impl>::initStage()
343{
344 // Setup PC and nextPC with initial state.
345 for (ThreadID tid = 0; tid < numThreads; tid++) {
346 pc[tid] = cpu->pcState(tid);
347 fetchOffset[tid] = 0;
348 macroop[tid] = NULL;
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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341void
342DefaultFetch<Impl>::initStage()
343{
344 // Setup PC and nextPC with initial state.
345 for (ThreadID tid = 0; tid < numThreads; tid++) {
346 pc[tid] = cpu->pcState(tid);
347 fetchOffset[tid] = 0;
348 macroop[tid] = NULL;
349 delayedCommit[tid] = false;
349 }
350
351 for (ThreadID tid = 0; tid < numThreads; tid++) {
352
353 fetchStatus[tid] = Running;
354
355 priorityList.push_back(tid);
356

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1065 // Add instruction to the CPU's list of instructions.
1066 instruction->setInstListIt(cpu->addInst(instruction));
1067
1068 // Write the instruction to the first slot in the queue
1069 // that heads to decode.
1070 assert(numInst < fetchWidth);
1071 toDecode->insts[toDecode->size++] = instruction;
1072
350 }
351
352 for (ThreadID tid = 0; tid < numThreads; tid++) {
353
354 fetchStatus[tid] = Running;
355
356 priorityList.push_back(tid);
357

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1066 // Add instruction to the CPU's list of instructions.
1067 instruction->setInstListIt(cpu->addInst(instruction));
1068
1069 // Write the instruction to the first slot in the queue
1070 // that heads to decode.
1071 assert(numInst < fetchWidth);
1072 toDecode->insts[toDecode->size++] = instruction;
1073
1074 // Keep track of if we can take an interrupt at this boundary
1075 delayedCommit[tid] = instruction->isDelayedCommit();
1076
1073 return instruction;
1074}
1075
1076template<class Impl>
1077void
1078DefaultFetch<Impl>::fetch(bool &status_change)
1079{
1080 //////////////////////////////////////////

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1107 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", tid);
1108
1109 fetchStatus[tid] = Running;
1110 status_change = true;
1111 } else if (fetchStatus[tid] == Running) {
1112 // Align the fetch PC so its at the start of a cache block.
1113 Addr block_PC = icacheBlockAlignPC(fetchAddr);
1114
1077 return instruction;
1078}
1079
1080template<class Impl>
1081void
1082DefaultFetch<Impl>::fetch(bool &status_change)
1083{
1084 //////////////////////////////////////////

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1111 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", tid);
1112
1113 fetchStatus[tid] = Running;
1114 status_change = true;
1115 } else if (fetchStatus[tid] == Running) {
1116 // Align the fetch PC so its at the start of a cache block.
1117 Addr block_PC = icacheBlockAlignPC(fetchAddr);
1118
1115 // Unless buffer already got the block, fetch it from icache.
1116 if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid]) && !inRom) {
1119 // If buffer is no longer valid or fetchAddr has moved to point
1120 // to the next cache block, AND we have no remaining ucode
1121 // from a macro-op, then start fetch from icache.
1122 if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid])
1123 && !inRom && !macroop[tid]) {
1117 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1118 "instruction, starting at PC %s.\n", tid, thisPC);
1119
1120 fetchCacheLine(fetchAddr, tid, thisPC.instAddr());
1121
1122 if (fetchStatus[tid] == IcacheWaitResponse)
1123 ++icacheStallCycles;
1124 else if (fetchStatus[tid] == ItlbWait)
1125 ++fetchTlbCycles;
1126 else
1127 ++fetchMiscStallCycles;
1128 return;
1124 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1125 "instruction, starting at PC %s.\n", tid, thisPC);
1126
1127 fetchCacheLine(fetchAddr, tid, thisPC.instAddr());
1128
1129 if (fetchStatus[tid] == IcacheWaitResponse)
1130 ++icacheStallCycles;
1131 else if (fetchStatus[tid] == ItlbWait)
1132 ++fetchTlbCycles;
1133 else
1134 ++fetchMiscStallCycles;
1135 return;
1129 } else if (checkInterrupt(thisPC.instAddr()) || isSwitchedOut()) {
1136 } else if ((checkInterrupt(thisPC.instAddr()) && !delayedCommit[tid])
1137 || isSwitchedOut()) {
1138 // Stall CPU if an interrupt is posted and we're not issuing
1139 // an delayed commit micro-op currently (delayed commit instructions
1140 // are not interruptable by interrupts, only faults)
1130 ++fetchMiscStallCycles;
1131 return;
1132 }
1133 } else {
1134 if (fetchStatus[tid] == Idle) {
1135 ++fetchIdleCycles;
1136 DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid);
1137 } else if (fetchStatus[tid] == Blocked) {

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1179
1180 TheISA::MachInst *cacheInsts =
1181 reinterpret_cast<TheISA::MachInst *>(cacheData[tid]);
1182
1183 const unsigned numInsts = cacheBlkSize / instSize;
1184 unsigned blkOffset = (fetchAddr - cacheDataPC[tid]) / instSize;
1185
1186 // Loop through instruction memory from the cache.
1141 ++fetchMiscStallCycles;
1142 return;
1143 }
1144 } else {
1145 if (fetchStatus[tid] == Idle) {
1146 ++fetchIdleCycles;
1147 DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid);
1148 } else if (fetchStatus[tid] == Blocked) {

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1190
1191 TheISA::MachInst *cacheInsts =
1192 reinterpret_cast<TheISA::MachInst *>(cacheData[tid]);
1193
1194 const unsigned numInsts = cacheBlkSize / instSize;
1195 unsigned blkOffset = (fetchAddr - cacheDataPC[tid]) / instSize;
1196
1197 // Loop through instruction memory from the cache.
1187 while (blkOffset < numInsts &&
1188 numInst < fetchWidth &&
1189 !predictedBranch) {
1198 // Keep issuing while we have not reached the end of the block or a
1199 // macroop is active and fetchWidth is available and branch is not
1200 // predicted taken
1201 while ((blkOffset < numInsts || curMacroop) &&
1202 numInst < fetchWidth && !predictedBranch) {
1190
1191 // If we need to process more memory, do it now.
1192 if (!(curMacroop || inRom) && !predecoder.extMachInstReady()) {
1193 if (ISA_HAS_DELAY_SLOT && pcOffset == 0) {
1194 // Walk past any annulled delay slot instructions.
1195 Addr pcAddr = thisPC.instAddr() & BaseCPU::PCMask;
1196 while (fetchAddr != pcAddr && blkOffset < numInsts) {
1197 blkOffset++;

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1227 ++fetchedInsts;
1228
1229 if (staticInst->isMacroop()) {
1230 curMacroop = staticInst;
1231 } else {
1232 pcOffset = 0;
1233 }
1234 } else {
1203
1204 // If we need to process more memory, do it now.
1205 if (!(curMacroop || inRom) && !predecoder.extMachInstReady()) {
1206 if (ISA_HAS_DELAY_SLOT && pcOffset == 0) {
1207 // Walk past any annulled delay slot instructions.
1208 Addr pcAddr = thisPC.instAddr() & BaseCPU::PCMask;
1209 while (fetchAddr != pcAddr && blkOffset < numInsts) {
1210 blkOffset++;

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1240 ++fetchedInsts;
1241
1242 if (staticInst->isMacroop()) {
1243 curMacroop = staticInst;
1244 } else {
1245 pcOffset = 0;
1246 }
1247 } else {
1235 // We need more bytes for this instruction.
1248 // We need more bytes for this instruction so blkOffset and
1249 // pcOffset will be updated
1236 break;
1237 }
1238 }
1239 if (curMacroop || inRom) {
1240 if (inRom) {
1241 staticInst = cpu->microcodeRom.fetchMicroop(
1242 thisPC.microPC(), curMacroop);
1243 } else {

--- 240 unchanged lines hidden --- 		1250 break;
1251 }
1252 }
1253 if (curMacroop || inRom) {
1254 if (inRom) {
1255 staticInst = cpu->microcodeRom.fetchMicroop(
1256 thisPC.microPC(), curMacroop);
1257 } else {

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